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2013 42nd International Conference on Parallel Processing (2013)
Lyon France
Oct. 1, 2013 to Oct. 4, 2013
ISSN: 0190-3918
pp: 893-900
Oliver Knodel , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
Andy Georgi , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
Patrick Lehmann , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
Wolfgang E. Nagel , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
Rainer G. Spallek , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
ABSTRACT
Heterogeneous systems consisting of general-purpose processors and different types of hardware accelerators are becoming more and more common in HPC systems. Especially Field Programmable Gate Arrays (FPGAs) provide an energy-efficient way to achieve high performance. Numerous application areas, including bio- and neuroinformatics, require enormous processing capability and employ simple computation cores, elementary data structures and algorithms highly suitable for FPGAs. To allow an efficient work with distributed FPGAs, it is necessary to provide a simple and scalable integration of these FPGAs in a common cluster architecture and to permit an easy access to these resources. Our approach enables a system-wide dynamic partitioning, a batch-based administration and the monitoring of FPGA resources. The system can easily be reconfigured to user-specific requirements and provides a high degree of flexibility and performance.
INDEX TERMS
Field programmable gate arrays, Random access memory, Hardware, Program processors, Computer architecture, Protocols, Tiles
CITATION

O. Knodel, A. Georgi, P. Lehmann, W. E. Nagel and R. G. Spallek, "Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures," 2013 42nd International Conference on Parallel Processing(ICPP), Lyon France, 2014, pp. 893-900.
doi:10.1109/ICPP.2013.106
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