2012 41st International Conference on Parallel Processing (2012)
Pittsburgh, PA, USA USA
Sept. 10, 2012 to Sept. 13, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICPP.2012.54
Many applications cache huge amount of data in RAM to achieve high performance. A good example is Memcached, a distributed-memory object-caching software. Memcached performance directly depends on the aggregated memory pool size. Given the constraints of hardware cost, power/thermal concerns and floor plan limits, it is difficult to further scale the memory pool by packing more RAM into individual servers, or by expanding the server array horizontally. In this paper, we propose an SSD-Assisted Hybrid Memory that expands RAM with SSD to make available a large amount of memory. Hybrid memory works as an object cache and it manages resource allocation at object granularity, which is more efficient than allocation at page granularity. It leverages the SSD fast random read property to achieve low latency object access. It organizes SSD into a log-structured sequence of blocks to overcome SSD writing anomalies. Compared to alternatives that use SSD as a virtual memory swap device, hybrid memory reduces the random access latency by 68% and 72% for read and write operations, and improves operation throughput by 15.3 times. Additionally, it reduces write traffic to SSD by 81%, which implies a 5.3 times improvement in SSD lifetime. We have integrated our hybrid memory design into Memcached. Our experiments indicate a 3.7X reduction in Memcached Get operation latency and up to 5.3X improvement in operation throughput. To the best of our knowledge, this paper is the first work that integrates the cutting edge SSD and InfiniBand-verbs into Memcached to accelerate its performance.
Random access memory, Servers, Indexes, Memory management, Slabs, Ash, High Performance Network, SSD, Virtual memory, Memcached
X. Ouyang et al., "SSD-Assisted Hybrid Memory to Accelerate Memcached over High Performance Networks," 2012 41st International Conference on Parallel Processing(ICPP), Pittsburgh, PA, USA USA, 2012, pp. 470-479.