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2009 International Conference on Parallel Processing (2009)
Vienna, Austria
Sept. 22, 2009 to Sept. 25, 2009
ISSN: 0190-3918
ISBN: 978-0-7695-3802-0
pp: 132-139
ABSTRACT
The building blocks of emerging Petascale massively parallel processing (MPP) systems are multi-core processors with four or more cores as a single processing element and a customized network interface. The resulting memory and communication hierarchy of these platforms are now exposed to application developers and end users by creating a hierarchical or multi-core aware message-passing (MPI) programming interface and by providing a handful of runtime, tunable parameters that allows mapping and control of MPI tasks and message handling. We characterize performance of MPI communication patterns and present strategies for optimizing applications performance on Cray XT series systems that are composed of contemporary AMD processors and a proprietary network infrastructure. We highlight dependencies in its memory and network subsystems, which could influence production-level applications performance. We demonstrate that MPI micro-benchmarks could mislead an application developer or end user since these benchmarks often do not expose the interplay between memory allocation and usage in the user space, which depends on the number of tasks or cores and workload characteristics. Our studies show performance improvements compared to the default options for our target scientific benchmarks and production-level applications.
INDEX TERMS
High performance computing, message passing communication, runtime systems, performance evaluation, scientific applications
CITATION

S. R. Alam, R. Barrett, S. Poole and J. Kuehn, "Performance Characterization of a Hierarchical MPI Implementation on Large-scale Distributed-memory Platforms," 2009 International Conference on Parallel Processing(ICPP), Vienna, Austria, 2009, pp. 132-139.
doi:10.1109/ICPP.2009.51
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