The Community for Technology Leaders
Proceedings International Conference on Parallel Processing (2002)
Vancouver, B.C., Canada
Aug. 18, 2002 to Aug. 21, 2002
ISSN: 0190-3918
ISBN: 0-7695-1677-7
pp: 409
J. C. Sancho , Universidad Politècnica de Valencia
A. Robles , Universidad Politècnica de Valencia
J. Flich , Universidad Politècnica de Valencia
P. López , Universidad Politècnica de Valencia
J. Duato , Universidad Politècnica de Valencia
<p>The InfiniBand Architecture (IBA) defines a switch-based network with point-to-point links whose topology is arbitrarily established by the customer. Often, the interconnection pattern is irregular, which complicates routing and deadlock avoidance. Current routing algorithms for NOWs, either achieve a low network performance, such as the up*/down* routing scheme, or cannot be implemented on IBA networks. IBA switches provide support for several virtual lanes, but they are primarily intended for QoS. Hence, its use for other purposes, like deadlock avoidance or performance improvement, should be limited.</p> <p>In this paper, we propose a simple and effective methodology for designing deadlock-free routing strategies that are able to route packets through minimal paths in InfiniBand networks. This methodology can meet the trade-off between network performance and the number of resources dedicated to deadlock avoidance. Evaluation results show that the resulting routing strategies significantly outperform up*/down* routing. In particular, throughput improvement ranges, on average, from 1:33 for small networks to 4:05 for large networks. Also, it is shown that just two virtual lanes and three service levels are enough to achieve more than 80% of the throughput improvement achieved by the best proposed routing strategy (the one that always provides minimal paths without limiting the number of resources).</p>

A. Robles, J. C. Sancho, P. López, J. Flich and J. Duato, "Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks," Proceedings International Conference on Parallel Processing(ICPP), Vancouver, B.C., Canada, 2002, pp. 409.
86 ms
(Ver 3.3 (11022016))