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Proceedings 2000 International Conference on Parallel Processing (2000)
Toronto, Canada
Aug. 21, 2000 to Aug. 24, 2000
ISSN: 0190-3918
ISBN: 0-7695-0768-9
pp: 77
Seon Wook Kim , Purdue University
Rudolf Eigenmann , Purdue University
ABSTRACT
We present a new software scheme, called compiler-assisted I-cache prediction (CIP) for energy reduction in instruction caches. With the help of compiler-supplied information, the processor is able to turn off substantial portions of the I-cache. The necessary cache sets are only turned on during the execution of individual code sections. The CIP scheme is based on the processor's ability to predict code sections that are about to execute and on the compiler's ability to precisely inform the hardware about the size of these code sections. Our techniques grew out of work with optimizing compilers for speculative parallel microarchitectures. The use of this target machine class is further motivated by the fact that speculative processors have the potential to overcome limitations in the compiler parallelization of many applications, especially non-numerical programs. Speculative microarchitectures are also among the most promising emerging architectures that can take advantage of the ever-increasing levels of chip integration. We will show that our new techniques can lead up to 90% I-cache energy savings in general-purpose applications without significant execution overhead. We believe that this is a substantial step towards the goal of making such chips integral parts of mobile computing devices, such as laptops, palm tops, and cellular phones.
INDEX TERMS
energy saving, speculative microarchitecture, compiler, instruction cache, branch prediction
CITATION

S. W. Kim and R. Eigenmann, "Compiler Techniques for Energy Saving in Instruction Caches of Speculative Parallel Microarchitectures," Proceedings 2000 International Conference on Parallel Processing(ICPP), Toronto, Canada, 2000, pp. 77.
doi:10.1109/ICPP.2000.876081
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