The Community for Technology Leaders
2013 42nd International Conference on Parallel Processing (1994)
North Carolina State University
Aug. 15, 1994 to Aug. 19, 1994
ISBN: 0-8493-2493-9
TABLE OF CONTENTS
Introduction

Preface (PDF)

pp. xvii

Keynote Speakers (PDF)

pp. xviii

List of Referees (PDF)

pp. xx-xxii
Session 1A: Interconnection Networks (I)

Multistage Interconnection Networks with Multiple Outlets (Abstract)

Hideharu Amano , Keio University, Japan
Toshihiro Hanawa , Keio University, Japan
Yoshifumi Fujikawa , Keio University, Japan
pp. 1-8

Performance Analysis of Combining Multistage Interconnection Networks (Abstract)

Sheldon Wong , The Pennsylvania State University, USA
Chita R. Das , The Pennsylvania State University, USA
Prasant Mohapatra , Iowa State University, USA
pp. 13-16

A General Inside-Out Routing Algorithm for a Class of Rearrangeable Networks (Abstract)

Seung-Woo Seo , The Pennsylvania State University, USA
Tse-yun Feng , The Pennsylvania State University, USA
pp. 17-20

Strategies for the Massively Parallel Simulation of Interconnection Networks (Abstract)

M. Jurczyk , Institute for Microelectronics Stuttgart, Germany
S. Abraham , Purdue University, USA
R. Born , NCR Corporation, USA
H.J. Siegel , Purdue University, USA
T. Schwederski , Institute for Microelectronics Stuttgart, Germany
pp. 21-25
Session 2A: Static Networks

Performance and Reliability of the Multistage Bus Network (Abstract)

Laxmi N. Bhuyan , Texas A & M University, USA
Ashwini K. Nanda , Texas Instruments, USA
Tahsin Askar , Texas A & M University, USA
pp. 26-33

Theory of Generalized Branch and Combine Clock Networks (Abstract)

Priyalal Kulasinghe , Louisiana State University, USA
Ahmed El-Amawy , Louisiana State University, USA
pp. 34-37

Continuum: A Hybrid Time/Space Communications Paradigm for k-ary n-cubes (Abstract)

Andrew C. Flavell , University of Tokushima, Japan
Yoshizo Takahashi , University of Tokushima, Japan
pp. 38-41

Analysis of Interconnection Networks Based on Cayley Graphs of Strong Generating Sets (Abstract)

S. Lakshmivarahan , University of Oklahoma, USA
S.K. Dhall , University of Oklahoma, USA
Jen-peng Huang , University of Oklahoma, USA
pp. 42-45

A Comparative Study of Star Graphs and Rotator Graphs (Abstract)

Vipin Chaudhary , Wayne State University, USA
Subburajan Ponnuswamy , Wayne State University, USA
pp. 46-50
Session 3A: Hierarchical Networks

Efficient Routing and Broadcasting in Recursive Interconnection Networks (Abstract)

Donald K. Friesen , Texas A & M University, USA
Arkady Kanevsky , University of Southern Mississippi, USA
Ronald Fernandes , Texas A & M University, USA
pp. 51-58

A Class of Static and Dynamic Hierarchical Interconnection Networks (Abstract)

Peter Thomas Breznay , University of Denver, USA
Mario Alberto Lopez , University of Denver, USA
pp. 59-62

Comparison of Mesh and Hierarchical Networks for Multiprocessors (Abstract)

Hong Jiang , University of Nebraska-Lincoln, USA
V. Carl Hamacher , Queen's University, Canada
pp. 67-71

Computational Properties of Mesh Connected Trees: Versatile Architectures for Parallel Computation (Abstract)

Antonio Fernandez , University of Southwestern Louisiana, USA
Kemal Efe , University of Southwestern Louisiana, USA
pp. 72-76
Session 4A: Novel Architectures

EXECUBE-A New Architecture for Scaleable MPPs (Abstract)

Peter M. Kogge , Loral Federal Systems - Owego, USA
pp. 77-84

Programming with Functional Memory (Abstract)

Richard Halverson, Jr. , University of Hawaii at Manoa, USA
Art Lew , University of Hawaii at Manoa, USA
pp. 85-92

Dynamic Barrier Architecture for Multi-Mode Fine-Grain Parallelism Using Conventional Processors (Abstract)

H.G. Dietz , Purdue University, USA
J.B. Sponaugle , Purdue University, USA
W.E. Cohen , Purdue University, USA
pp. 93-96

Design and Evaluation of a Multiprocessor Architecture with Decentralized Control (Abstract)

Peter J. Zievers , The University of Texas at Austin, USA
Hsiao-chen Chung , The University of Texas at Austin, USA
Yin-Kuan Lin , The University of Texas at Austin, USA
Chuan-lin Wu , The University of Texas at Austin, USA
James Rakes , The University of Texas at Austin, USA
pp. 97-100
Session 5A: Interconnection Networks (II)

Nonblocking Operation of Asymmetrical Clos Networks (Abstract)

Fotios K. Liotopoulos , University of Wisconsin-Madison, USA
Suresh Chalasani , University of Wisconsin-Madison, USA
pp. 101-108

A New Tag Scheme and Its Tree Representation for a Shuffle-Exchange Network (Abstract)

Tse-yun Feng , The Pennsylvania State University, USA
Yanggon Kim , The Pennsylvania State University, USA
pp. 109-112

On the Rearrangeability of Reverse Shuffle/Exchange Networks (Abstract)

B. Park , Texas A&M University, USA
K. Watson , Texas A&M University, USA
pp. 113-116

SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture (Abstract)

Hideharu Amano , Keio University, Japan
Luo Zhou , Keio University, Japan
Jun-ichi Yamato , Keio University, Japan
Masashi Sasahara , Keio University, Japan
Jun Terada , Keio University, Japan
Satoshi Ogura , Keio University, Japan
Kalidou Gaye , Keio University, Japan
pp. 117-120

On Sorting Multiple Bitonic Sequences (Abstract)

Kenneth E. Batcher , Kent State University, USA
De-Lei Lee , York University, Canada
pp. 121-125
Session 6A: Wormhole Routing

Sequencing of Concurrent Communication Traffic in a Mesh Multicomputer with Virtual Channels (Abstract)

Bing-rung Tsai , The University of Michigan, USA
Kang G. Shin , The University of Michigan, USA
pp. 126-133

Optimal Multicast Communication in Wormhole-Routed Torus Networks (Abstract)

Philip K. McKinley , Michigan State University, USA
Betty H.C. Cheng , Michigan State University, USA
David F. Robinson , Michigan State University, USA
pp. 134-141
Session 7A: Cache (I)

A Distributed Cache Coherence Protocol for Hypercube Multiprocessors (Abstract)

Akhilesh Kumar , Texas A&M University, USA
Yeimkunn Chang , Texas A&M University, USA
Laxmi N. Bhuyan , Texas A&M University, USA
pp. 150-157

An Integrated Methodology for the Verification of Directory-Based Cache Protocols (Abstract)

Fong Pong , Lund University, Sweden
Michel Dubois , University of Southern California, Los Angeles, USA
pp. 158-165

Reducing the Write Traffic for a Hybrid Cache Protocol (Abstract)

Per Stenstrom , Lund University, Sweden
Fredrik Dahlgren , Lund University, Sweden
pp. 166-173
Session 8A: Communication Issues

Latency Analyses of CC-NUMA and CC-COMA Rings (Abstract)

Yong Yan , The University of Texas at San Antonio, USA
Xiaodong Zhang , The University of Texas at San Antonio, USA
pp. 174-181

Deadlock-free Asynchronous Communication Strategies for Unstructured Computations on iPSC/860 (Abstract)

Vijay K. Naik , IBM T.J. Watson Research Center, USA
Sesh Venugopal , Rutgers University, USA
pp. 187-190

A Comparative Performance Study of an Interconnection Cached Network (Abstract)

Eugen Schenfeld , NEC Research Institute, Inc., USA
Vipul Gupta , Rutgers University, USA
pp. 191-195

Hybrid Multiprocessing in OPTIMUL: A Multiprocessor for Distributed and Shared Memory Multiprocessing with WDM Optical Fiber Interconnections (Abstract)

Kanad Ghose , State University of New York at Binghamton, USA
Nitin Singhvi , State University of New York at Binghamton, USA
R. Kym Horsell , State University of New York at Binghamton, USA
pp. 196-199
Session 9A: Memory Systems

A Shared Memory Environment for Hypercubes (Abstract)

Chita R. Das , The Pennsylvania State University, USA
Amit Agarwala , The Pennsylvania State University, USA
pp. 200-207

Optimizing IPC Performance for Shared-Memory Multiprocessors (Abstract)

Benjamin Gamsa , University of Toronto, Canada
Michael Stumm , University of Toronto, Canada
Orran Krieger , University of Toronto, Canada
pp. 208-211

Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories (Abstract)

Lizyamma Kurian , University of South Florida, USA
Paul T. Hulina , The Pennsylvania State University, USA
Lee D. Coraor , The Pennsylvania State University, USA
Bermjae Choi , University of South Florida, USA
pp. 212-219

PSIM: Periodically Shifted Interleaved Memory System (Abstract)

Hee Yong Youn , The University of Texas at Arlington, USA
Jae Young Lee , The University of Texas at Arlington, USA
pp. 220-223
Session 10A: VLSI Based Architecture

An Efficient VLSI Architecture for Template Matching (Abstract)

Satish Venugopal , University of South Florida, USA
N. Ranganathan , University of South Florida, USA
pp. 224-231

Block Data Processing Using Commercial Processors (Abstract)

Kenneth N. Ellis , North Carolina State University, USA
Winser E. Alexander , North Carolina State University, USA
pp. 232-235

Rank Order Filtering on an Array with Faulty Processors (Abstract)

Jose Salinas , Texas A&M University, USA
Fabrizio Lombardi , Texas A&M University, USA
pp. 236-240

Image Correlation: A Case Study to Examine SIMD/MIMD Trade-offs for Scalable Parallel Algorithms (Abstract)

James B. Armstrong , Sarnoff Real Time Corporation , USA
Kenneth H. Casey , Purdue University, USA
Mark A. Nichols , NCR Corporation, USA
Howard Jay Siegel , Purdue University, USA
pp. 241-245

Fault-Tolerant Routing Algorithms for a Massively Parallel Machine (Abstract)

C. Robach , LGI-IMAG, France
G. Mazare , LGI-IMAG, France
C. Aktouf , LGI-IMAG, France
pp. 246-249
Session 11A: Cache (II)

A One's Complement Cache Memory (Abstract)

Qing Yang , University of Rhode Island, USA
Sridhar Adina , University of Rhode Island, USA
pp. 250-257

Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? (Abstract)

Ricardo Bianchini , University of Rochester, USA
Thomas J. LeBlanc , University of Rochester, USA
pp. 258-262

Compiler Optimization Technique for Data Cache Prefetching Using a Small CAM Array (Abstract)

Chi-Hung Chi , The Chinese University of Hong Kong, Hong Kong
pp. 263-266

Degenerate Sharing (Abstract)

Brett D. Fleisch , University of California, Riverside, USA
Randall L. Hyde , University of California, Riverside, USA
pp. 267-270

Error Recovery in Parallel Systems of Pipelined Processors with Caches (Abstract)

Shih-Chang Wang , National Taiwan University, Taiwan
Jeng-Ping Lin , National Taiwan University, Taiwan
Sy-Yen Kuo , National Taiwan University, Taiwan
pp. 271-274
Session 12A: Multithreading/VLIW

Performance of Switch Blocking on Multithreaded Architectures (Abstract)

K. Gopinath , Indian Institute of Science, India
Krishna Narasimhan M.K. , Indian Institute of Science, India
B.H. Lim , MIT
pp. 275-284

An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures (Abstract)

W. Kent Fuchs , University of Illinois at Urbana-Champaign, USA
Wen-Mei W. Hwu , University of Illinois at Urbana-Champaign, USA
Shyh-Kwei Chen , University of Illinois at Urbana-Champaign, USA
pp. 285-292

Performance Issues of a Superscalar Microprocessor (Abstract)

Nader Bagherzadeh , University of California, Irvine, USA
Steven Wallace , University of California, Irvine, USA
pp. 293-297

Partitioning of Variables for Multiple-Register-File VLIW Architectures (Abstract)

Nikil Dutt , University of California, Irvine, USA
Andrea Capitanio , Universita' di Padova, Italy
Alexandru Nicolau , University of California, Irvine, USA
pp. 298-301
Author Index

Author Index (PDF)

pp. xxiii
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