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2013 42nd International Conference on Parallel Processing (1993)
Syracuse University
Aug. 16, 1993 to Aug. 20, 1993
ISBN: 0-8493-8983-6
TABLE OF CONTENTS
Introduction

Preface (PDF)

pp. ix
SESSION 1A: CACHE MEMORY

Automatic Partitioning of Parallel Loops for Cache-Coherent Multiprocessors (Abstract)

David Kranz , Massachusetts Institute of Technology
Anant Agarwal , Massachusetts Institute of Technology
Venkat Natarajan , Motorola Cambridge Research Center, Cambridge, MA
pp. 2-11

Techniques to Enhance Cache Performance Across Parallel Program Sections (Abstract)

J.H. Tang , IBM Advanced Workstation Systems, Austin, TX
K. So , IBM Advanced Workstation Systems, Austin, TX
J.K. Peir , Computer & Communication Lab., Industr. Tech. Res. Inst., Taiwan ROC
pp. 12-19

A Generational Algorithm to Multiprocessor Cache Coherence (Abstract)

Tzi-cker Chiueh , State University of New York at Stony Brook
pp. 20-24

Semi-unified Caches (Abstract)

Andre Seznec , IRISA/INRIA Campus de Beaulieu, Cedex, France
Nathalie Drach , IRISA/INRIA Campus de Beaulieu, Cedex, France
pp. 25-28
SESSION 2A: PROCESSOR AND COMMUNICATION ARCHITECTURE

Dependence Analysis and Architecture Design for Bit-Level Algorithms (Abstract)

Benjamin W. Wah , University of Illinois, Urbana-Champaign
Weijia Shang , University of Southwestern Louisiana
pp. 30-38

ATOMIC: A Low-Cost, Very-High-Speed, Local Communication Architecture (Abstract)

Danny Cohen , USC/Information Sciences Institute, Marina del Rey, CA
Gregory Finn , USC/Information Sciences Institute, Marina del Rey, CA
pp. 39-46

Reconfigurable Branch Processing Strategy in Super-scalar Microprocessors (Abstract)

Chuan-lin Wu , University of Texas at Austin, Austin, TX
Hsiao-Chen Chung , University of Texas at Austin, Austin, TX
Terence M. Potter , University of Texas at Austin, Austin, TX
pp. 47-50

Exploiting Spatial and Temporal Parallelism in the Multithreaded Node Architecture Implemented on Superscalar RISC Processors (Abstract)

D. J. Hwang , SungKyunKwan University
S. H. Cho , Seoul National University
Y. D. Kim , Seoul National University
S. Y. Han , Seoul National University
pp. 51-54
SESSION 3A: MEMORY

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors (Abstract)

Michel Dubois , University of Southern California
Per Stenstrom , Lund University
Fredrik Dahlgren , Lund University
pp. 56-63

Assigning Sites to Redundant Clusters in a Distributed Storage System (Abstract)

W. Kent Fuchs , University of Illinois
Antoine N. Mourad , University of Illinois
Daniel G. Saab , University of Illinois
pp. 64-71

Balanced Distributed Memory Parallel Computers (Abstract)

F. Delaplace , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
D. Etiemble , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
J-L Giavitto , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
F. Cappello , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
V. Neri , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
J-L Bechennec , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
C. Germain , LRI - UA 410 CNRS, Universite Paris Sud, Cedex, France
pp. 72-76

A Novel Approach to the Design of Scalable Shared-Memory Multiprocessors (Abstract)

Honda Shing , Unisys Corporation, San Jose, CA
Lionel M. Ni , Michigan State University
pp. 77-81
SESSION 4A: GRAPH-THEORETIC INTERCONNECTION STRUCIZTRES

Incomplete Star Graph : An Economical Fault-tolerant Interconnection Network (Abstract)

CP. Ravikumar , Indian Institute of Technology-
A. Kuchlous , Indian Institute of Technology-
G. Manimaran , National Informatics Center, New Delhi, INDIA
pp. 83-90

The Star Connected Cycles: A Fixed-Degree Network For Parallel Processing (Abstract)

Shahram Latifi , University of Nevada, Las Vegas
Nader Bagherzadeh , University of California, Irvine - Irvine, CA
Marcelo Moraes de Azevedo , University of California, Irvine - Irvine, CA
pp. 91-95

Empirical Evaluation of Incomplete Hypercube Systems (Abstract)

Nian-Feng Tzeng , University of Southwestern Louisiana
pp. 96-99

A Distributed Multicast Algorithm for Hypercube Multicomputers (Abstract)

Jyh-Charn Liu , Texas A&M University
Hung-Ju Lee , Texas A&M University
pp. 100-104

A Generalized Bitonic Sorting Network (Abstract)

Kenneth E. Batcher , Kent State University
Kathy J. Liszka , Kent State University
pp. 105-108
SESSION 5A: HYPERCUBE

A Lazy Scheduling Scheme for Improving Hypercube Performance (Abstract)

Chita R. Das , Pennsylvania State University
Chansu Yu , Pennsylvania State University
Jong Kim , POSTECH, Korea
Prasant Mohapatra , Pennsylvania State University
pp. 110-117

Fault Tolerant Subcube Allocation in Hypercubes (Abstract)

Yeimkuan Chang , Texas A&M University
Laxmi N. Bhuyan , Texas A&M University
pp. 132-136
SESSION 6A: ARCHITECTURE

Performance of Redundant Disk Array Organizations in Transaction Processing Environments (Abstract)

Antoine N. Mourad , University of Illinois
Daniel G. Saab , University of Illinois
W. Kent Fuchs , University of Illinois
pp. 138-145

WDM Cluster Ring: A Low-Complexity Partitionable Reconfigurable Processor Interconnection Structure (Abstract)

KHALED A. ALY , State University of New York at Buffalo
PATRICK W. DOWD , State University of New York at Buffalo
pp. 150-153

A Scalable Optical Interconnection Network for Fine-Grain Parallel Architectures (Abstract)

Matthias Grossglauser , Georgia Institute of Technology
D. Scott Wills , Georgia Institute of Technology
pp. 154-157

Bus-Based Tree Structures for Efficient Parallel Computation (Abstract)

O. M. Dighe , Louisiana State University, Baton Rouge, LA
R. Vaidyanathan , Louisiana State University, Baton Rouge, LA
S. Q. Zheng , Louisiana State University, Baton Rouge, LA
pp. 158-161
SESSION 7A: CACHE MEMORY

Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches (Abstract)

Yarsun Hsu , IBM T. J. Watson Research Center, NY
Yew-Huey Liu , IBM T. J. Watson Research Center, NY
C. Eric Wu , IBM T. J. Watson Research Center, NY
pp. 163-170

Parallel Cache Simulation on Multiprocessor Workstattions (Abstract)

Luis Barriga , Royal Institute of Technology, Sweden
Rassul Ayani , Royal Institute of Technology, Sweden
pp. 171-174

A Chained-Directory Cache Choerence Protocol for Multiprocessors (Abstract)

Soon M. Chung , Wright State University
Longxue Li , Wright State University
pp. 175-179

Evaluating the impact of cache interferences on numerical codes (Abstract)

0. Temam , University of Leiden, INRIA, IRISA
W. Jalby , University of Leiden, INRIA, IRISA
C. Fricker , University of Leiden, INRIA, IRISA
pp. 180-183

Performance Evaluation of Memory Caches in Multiprocessors (Abstract)

Yung-Chin Chen , MIPS Technologies, Inc., Silicon Graphics, Inc., Mountain View, CA
Alexander V. Veidenbaum , University of Illinois at Urbana-Champaign
pp. 184-187
SESSION 8A: PERFORMANCE EVALUATION

Transmission Times in Buffed Full-Crossbar Communication Networks with Cyclic Arbitration (Abstract)

A.J. Field , Imperial College of Science, UK
P.G. Harrison , Imperial College of Science, UK
pp. 189-196

Experimental Validation of a Performance Model for Simple Layered Task Systems (Abstract)

Athar B. Tayyab , University of Iowa, Iowa City, IA
Jon G. Kuhl , University of Iowa, Iowa City, IA
pp. 197-201

Performance Evaluation of SIMD Processor Architectures Using Pairwise Multiplier Recoding (Abstract)

Edward W. Davis , North Carolina State University
Todd C. Marek , North Carolina State University
pp. 202-205

A Queuing Model for Finite-Buffered Multistage Interconnection Networks (Abstract)

Prasant Mohapatra , Pennsylvania State University
Chita R. Das , Pennsylvania State University
pp. 210-213

Composite Performance and Reliability Analysis for Hypercube Systems (Abstract)

Samir M. Koriem , Indian Institute of Science, Bangalore-, INDIA
pp. 214-217
SESSION 9A: DISTRIBUTED SYSTEMS AND ARCHITECTURE

Estimation of Execution times on Heterogeneous Supercomputer Architectures (Abstract)

Arif Ghafoor , Purdue University
Ishfaq Ahmad , Hong Kong University
Jaehyung Yang , Purdue University
pp. 219-226

A Hybrid Shared Memory/Message Passing Parallel Machine (Abstract)

Mary K. Vernon , University of Wisconsin-Madison
Matthew I. Frank , University of Wisconsin-Madison
pp. 232-236

Scalability Study of the KSR-1 (Abstract)

S. Ravikumar , Georgia Institute of Technology, Atlanta, GA
Umakishore Ramachandran , Georgia Institute of Technology, Atlanta, GA
Jeyakumar Muthukumarasamy , Georgia Institute of Technology, Atlanta, GA
Gautam Shah , Georgia Institute of Technology, Atlanta, GA
pp. 237-240

Personalized Communication Avoiding Node Contention on Distributed Memory Systems (Abstract)

Jhy-Chun Wang , Syracuse University
Manoj Kumar , IBM T.J. Watson Research Center, NY
Sanjay Ranka , Syracuse University
pp. 241-244
SESSION 10A: MEMORY AND DISKS

Design of Algorithm-Based Fault Tolerant Systems with In-System Checks (Abstract)

Niraj K. Jha , Princeton University
Shalini Yajnik , Princeton University
pp. 246-253

A Cache Coherence Protocol for MIN-Based Multiprocessors With Limited Inclusion (Abstract)

Chita R. Das , Pennsylvania State University
Matthew J. Thazhuthaveetil , Pennsylvania State University
Mazin S. Yousif , Pennsylvania State University
pp. 254-257

Impact of Memory Contention on Dynamic Scheduling on Numa Multiprocessors (Abstract)

T. Montaut , IRISA, Campus de Beaulieu, Cedex, France
L. Kervella , IRISA, Campus de Beaulieu, Cedex, France
M. D. Durand , Bellcore, Morristown, NJ
W. Jalby , MASI, Universit6 de Versailles, Cedex, France
pp. 258-262

Reliability Evaluation of Disk Array Architectures (Abstract)

Prithviraj Banerjee , University of Illinois at Urbana-Champaign
John A. Chandy , University of Illinois at Urbana-Champaign
pp. 263-267

Prime-way Interleaved Memory (Abstract)

De-Lei Lee , York University, Ontario Canada
pp. 268-272
SESSION 11A: ROUTING ALGORITHMS AND RING, BUS STRUCTURES

Reducing the Effect of Hot Spots by Using a Multipath Network (Abstract)

Mu-Cheng Wang , Purdue University
Howard Jay Siegel , Purdue University
Mark A. Nichols , Purdue University
Seth Abraham , Purdue University
pp. 274-281

Hardware Support for Fast Reconfigurability in Progress Arrays (Abstract)

P. Baglietto , University of Genova, Italy
M. Maresca , University of Genova, Italy
H. Li , University of Genova, Italy
pp. 282-289

Closed Form Solutions for Bus and Tree Networks of Processors Load Sharing A Divisible Job (Abstract)

S. Bataineh , Jordan University of Science and Technology
T. G. Robertazzi , Jordan University of Science and Technology
T. Hsiung , Jordan University of Science and Technology
pp. 290-293

The Message Flow Model for Routing in Wormhole-Routed Networks (Abstract)

Xiaola Lin , Michigan State University
Lionel M. Ni , Michigan State University
Philip K. McKinley , Michigan State University
pp. 294-297
SESSION 12A: GRAPH-THEORETIC INTERCONNECTION STRUCTURJ3S

Generalized Fibonacci Cubes (Abstract)

W. J. Hsu , Nanyang Technological University, Singapore
M. J. Chung , Nanyang Technological University, Singapore
pp. 299-302

HMIN : A New Method for Hierarchical Interconnection of Processors (Abstract)

Dharma P. Agrawal , North Carolina State University
Yashovardhan R. Potlapalli , North Carolina State University
pp. 303-306

Tightly Connected Hierarchical Interconnection Networks for Parallel Processors (Abstract)

Peter Thomas Breznay , University of Denver, Denver CO
Mario Alberto Lopez , University of Denver, Denver CO
pp. 307-310

The Folded Petersen Network : A New Communication-Efficient Multiprocessor Topology (Abstract)

Sabine Ohring , University of Wurzburg
Sajal K. Das , University of North Texas, Denton, TX
pp. 311-314

Hierarchical WK-Recursive Topologies for Multicomputer Systems (Abstract)

Ronald Fernandes , Texas A&M University, TX
Arkady Kanevsky , Texas A&M University, TX
pp. 315-318

Substructure Allocation in Recursive Interconnection Networks (Abstract)

Arkady Kanevsky , Texas A&M University
Ronald Fernandes , Texas A&M University
pp. 319-322
SESSION 13A: ARCHITECTURE

Coherence, Synchronization and State-sharing in Distributed Shared-memory Applications (Abstract)

Richard J. LeBlanc , Georgia Institute of Technology
R. Ananthanarayanan , Georgia Institute of Technology
Mustaque Ahamad , Georgia Institute of Technology
pp. 324-331

A Characterization of Scalable Shared Memories (Abstract)

Gil Neiger , Georgia Institute of Technology
Prince Kohli , Georgia Institute of Technology
Mustaque Ahamad , Georgia Institute of Technology
pp. 332-335

P3M: A Virtual Machine Approach to Massively Parallel Computing (Abstract)

Fabrizio Baiardi , Universita di Pisa, Italy
Mehdi Jazayeri , Universita di Pisa, Italy
pp. 340-344

Pipeline Processing of Multi-Way Queries in Shared-Memory Systems (Abstract)

Hongjun LU , National University of Singapore
Kian-Lee TAN , National University of Singapore
pp. 345-348
Author Index

Author Index (PDF)

pp. 351
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