Computer and Information Science, ACIS International Conference on (2007)
July 11, 2007 to July 13, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICIS.2007.172
Xuemei Zhao , Flinders University, Australia
Karl Sammut , Flinders University, Australia
Fangpo He , Flinders University, Australia
Shaowen Qin , Flinders University, Australia
Cache access latency and efficient usage of on-chip capacity are critical factors that affect the performance of the chip multiprocessor (CMP) architecture. In this paper, we propose a SPS2 cache architecture and cache coherence protocol for snooping-based CMP, in which each processor has both private and shared L2 cache to balance latency and capacity. Our protocol is expressed in a new state graph form, through which we prove our protocol by formal verification method. Simulation experiments shows that the SPS2 structure outperforms private L2 and shared L2 structure.
S. Qin, X. Zhao, K. Sammut and F. He, "Split Private and Shared L2 Cache Architecture for Snooping-based CMP," 2007 International Conference on Computer and Information Science(ICIS), Melbourne, Qld., 2007, pp. 900-905.