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Innovative Computing ,Information and Control, International Conference on (2006)
Beijing, China
Aug. 30, 2006 to Sept. 1, 2006
ISBN: 0-7695-2616-0
pp: 609-612
Jianying Peng , ZheJiang University, China
Xing Qin , ZheJiang University, China
Jian Yang , ZheJiang University, China
Xiaolang Yan , ZheJiang University, China
Xiexiong Chen , ZheJiang University, China
Bitstream parsing is a basic task in video decoding systems. With the development of video compression standards, the trend of the VLSI architecture for bitstream parser is toward programmable. Due to the strong data-dependency and bit-level sequential operations, bitstream parsing is unsuitable to accelerate by general architectures, such as RISC, SIMD and VLIW processors. This paper proposes a programmable bitstream parser for multiple video coding standards on embedded RISC processors. The proposed design presents an extension instruction set to accelerate some kernel functions of bitstream parsing. As a result, the proposed bitstream parser can decode every syntax element per cycle. The synthesis result shows that at the clock constraint of 150MHz, the hardware cost is about 7K gates of logic and 2k byte RAM under a 0.18um CMOS technology.

J. Peng, J. Yang, X. Chen, X. Qin and X. Yan, "A Programmable Bitstream Parser for Multiple Video Coding Standards," First International Conference on Innovative Computing, Information and Control(ICICIC), Beijing, 2006, pp. 609-612.
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