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Formal Engineering Methods, International Conference on (2000)
York, England
Sept. 4, 2000 to Sept. 7, 2000
ISBN: 0-7695-0822-7
pp: 45
Arun Venkataraman , University of Cincinnati
Murali Rangarajan , University of Cincinnati
Perry Alexander , University of Kansas
ABSTRACT
As systems become increasingly complex, and existing methodologies become insufficient to handle the complexity, the design community is beginning to look at formal methods for a possible solution. Techniques involving limited use of formal techniques (such as semi-formal methods and equivalence checking) have given a glimpse of what full usage of formal techniques can achieve. For the use of formal methods to be a widely accepted methodology among designers, it must provide the designers with the capabilities of structuring specification in a manner similar to the structuring they are used to using with programming languages. In this paper, we provide a description of the structuring capabilities of VSPEC, a requirement specification language for VHDL. These capabilities include use of multiple pre- and post-condition pairs within a single specification and combination of specifications using common Boolean operators.
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CITATION

P. Alexander, M. Rangarajan and A. Venkataraman, "Composing Specifications in VSPEC," Formal Engineering Methods, International Conference on(ICFEM), York, England, 2000, pp. 45.
doi:10.1109/ICFEM.2000.873804
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