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Engineering of Complex Computer Systems, IEEE International Conference on (2011)
Las Vegas, Nevada USA
Apr. 27, 2011 to Apr. 29, 2011
ISBN: 978-0-7695-4381-9
pp: 338-343
ABSTRACT
Real-Time Embedded systems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taking into account the impact of the whole software, both the user code and the underlying run time environment. AADL allows one to precisely capture all of them. In this article, we evaluate the AADL modeling to define memory architectures, and then verification rules to assess that the memory is correctly dimensioned. We use the REAL domain-specific language to express memory requirements (such as layout or size) and then validate them on a case-study using the VxWorks real-time kernel.
INDEX TERMS
AADL, constraint language, REAL, architecture, verification, memory architecture
CITATION
Frank Singhoff, Jérôme Hugues, Stéphane Rubini, "Modeling and Verification of Memory Architectures with AADL and REAL", Engineering of Complex Computer Systems, IEEE International Conference on, vol. 00, no. , pp. 338-343, 2011, doi:10.1109/ICECCS.2011.40
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