2013 IEEE 29th International Conference on Data Engineering (ICDE) (2013)
Brisbane, Australia Australia
Apr. 8, 2013 to Apr. 12, 2013
C. Balkesen , Dept. of Comput. Sci., ETH Zurich, Zurich, Switzerland
J. Teubner , Dept. of Comput. Sci., ETH Zurich, Zurich, Switzerland
G. Alonso , Dept. of Comput. Sci., ETH Zurich, Zurich, Switzerland
M. T. Ozsu , Univ. of Waterloo, Waterloo, ON, Canada
The architectural changes introduced with multi-core CPUs have triggered a redesign of main-memory join algorithms. In the last few years, two diverging views have appeared. One approach advocates careful tailoring of the algorithm to the architectural parameters (cache sizes, TLB, and memory bandwidth). The other approach argues that modern hardware is good enough at hiding cache and TLB miss latencies and, consequently, the careful tailoring can be omitted without sacrificing performance. In this paper we demonstrate through experimental analysis of different algorithms and architectures that hardware still matters. Join algorithms that are hardware conscious perform better than hardware-oblivious approaches. The analysis and comparisons in the paper show that many of the claims regarding the behavior of join algorithms that have appeared in literature are due to selection effects (relative table sizes, tuple sizes, the underlying architecture, using sorted data, etc.) and are not supported by experiments run under different parameters settings. Through the analysis, we shed light on how modern hardware affects the implementation of data operators and provide the fastest implementation of radix join to date, reaching close to 200 million tuples per second.
Hardware, Probes, Latches, Partitioning algorithms, Tuning, Instruction sets, Algorithm design and analysis
C. Balkesen, J. Teubner, G. Alonso and M. T. Ozsu, "Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware," 2013 29th IEEE International Conference on Data Engineering (ICDE 2013)(ICDE), Brisbane, QLD, 2013, pp. 362-373.