Proceedings 21st International Conference on Distributed Computing Systems Workshops (2001)
Apr. 16, 2001 to Apr. 19, 2001
Jan-Derk Bakker , Delft University of Technology
Koen Langendoen , Delft University of Technology
Henk Sips , Delft University of Technology
Abstract: To ease the implementation of different wearable computers, we developed a low-power processor board (named LART) with a rich set of interfaces. The LART supports dynamic voltage scaling, so performance (and power consumption) can be scaled to match demands: 59-221 MHz, 106-640 mW. High-end wearables can be configured from multiple LARTs operating in parallel; alternatively, FPGA boards can be used for dedicated data-processing, which reduces power consumption significantly.
J. Bakker, K. Langendoen and H. Sips, "LART: Flexible, Low-Power Building Blocks for Wearable Computers," Proceedings 21st International Conference on Distributed Computing Systems Workshops(ICDCSW), Mesa, Arizona, 2001, pp. 0255.