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2017 IEEE International Conference on Computer Design (ICCD) (2017)
Boston, MA, USA
Nov. 5, 2017 to Nov. 8, 2017
ISSN: 1063-6404
ISBN: 978-1-5386-2254-4
pp: 581-584
ABSTRACT
Multi Level Cell (MLC) Spin Transfer Torque RAM (STT-RAM) provides higher density than Single Level Cell (SLC) STT-RAM by storing two digital bits in a single cell, and is proposed as a promising candidate for on-chip cache. However, MLC STT-RAM suffers from high write energy. We observe that general encoding methods, which map the frequent data patterns to the energy-efficient resistance states, cannot reduce the write energy of MLC STT-RAM. To reduce the write energy of MLC STT-RAM, we propose a novel encoding method, i.e., Encoding Separately (ES). The key idea of ES is to encode the hard bits and soft bits of MLCs separately. The hard bits are encoded for fewer hard-bit writes (hard transitions) and soft bits are encoded for fewer soft-bit writes (soft transitions). Specifically, existing encoding methods commonly used in SLC can be applied to MLC STT-RAM when encoding the two bits separately. We further apply two encoding methods for SLC to MLC STT-RAM through encoding separately, and experimental results show that the proposed scheme can reduce the writes to hard bits and soft bits by 28% and 16%, and achieve an energy reduction of 25%.
INDEX TERMS
cache storage, encoding, MRAM devices, random-access storage
CITATION

J. Xu, D. Feng, W. Tong, J. Liu and W. Zhou, "Encoding Separately: An Energy-Efficient Write Scheme for MLC STT-RAM," 2017 IEEE 35th International Conference on Computer Design (ICCD), Boston, MA, USA, 2018, pp. 581-584.
doi:10.1109/ICCD.2017.100
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