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2017 IEEE International Conference on Computer Design (ICCD) (2017)
Boston, MA, USA
Nov. 5, 2017 to Nov. 8, 2017
ISSN: 1063-6404
ISBN: 978-1-5386-2254-4
pp: 565-572
3D architectures are considered the most promising approach to continuously increasing memory density and reducing cost/bit for NAND flash memory by stacking more layers. However, 3D MLC flash memory brings two serious problems, referred to as cell-to-cell program disturbance and big block problem. To solve the disturbance problem for better reliability, we proposed a Disturbance Compensation Programming Scheme (DCPS). Based on quantitatively analyzing the disturbance from each direction in 3D flash memory, the scheme accordingly set the verify voltage (VVFY) a little lower than the original value when Incremental Step Pulse Programming (ISPP) is performed. After disturbance compensation, the threshold voltage of flash cells can shift towards the ideal distribution. Moreover, Read reference Voltage Shifting (RVS) and Artificial Compensation (AC) strategies on margin pages are introduced to adapt to the three-dimensional structures to further enhance reliability. To solve big block problem, Multiple-Level-Queue page allocation (MLQ) is proposed. We use multiple queues to filter the logical addresses of different update counts and choose different data blocks to respond. The stored data are gradually well organized and generate less data migration when performing garbage collection. Experimental results show that our design reduces the disturbed BER by at least 82% with respect to a FTL with traditional allocation and garbage collection scheme. Besides, we demonstrate MLQ can achieve more effective results than the state of the art scheme in the big block environment. The write amplification, I/O response time and the number of erasures are reduced by 31.2%, 22.2% and 14.6% on average, respectively.
flash memories, NAND circuits, reliability, storage management

Y. Feng, D. Feng, W. Tong, Y. Jiang and C. Liu, "Using Disturbance Compensation and Data Clustering (DC)2 to Improve Reliability and Performance of 3D MLC Flash Memory," 2017 IEEE 35th International Conference on Computer Design (ICCD), Boston, MA, USA, 2018, pp. 565-572.
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