DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory
2017 IEEE International Conference on Computer Design (ICCD) (2017)
Boston, MA, USA
Nov. 5, 2017 to Nov. 8, 2017
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2017.50
Resistive random access memory (RRAM) is promising to be used as high density storage-class memory by employing crossbar structure. However, the wire resistance in crossbar array causes the IR drop problem, which makes nonuniformity of write latency throughout the array. In large crossbar array, the write latency differs greatly even in the same row. Since the write latency of a region is determined by its slowest write-unit, the conventional group-by-row region partition and addressing scheme is suboptimal for improving the overall performance of RRAM. In this work, we present DAWS, a novel RRAM architecture that exploits intrinsic features of crossbar structure. We first build a circuit model to analyze the voltage distribution and write latency distribution in a crossbar array. Then we propose a voltage bias scheme to optimize write latency via minimizing the IR drop path. We further present block diagonal partition to narrow the variance of write latency within each region, thus the write latency of each region is reduced. Moreover, we provide block diagonal addressing to make the write latency monotonically increase with the physical address, which is in favor of address mapping and memory allocation. We also design diagonal writing and diagonal swapping to overlap SET and RESET operations by applying a particular voltage bias pattern that can exploit row level parallelism, thus the number of write operations is halved. The experimental results show that DAWS can reduce memory access latency by 24.0% and improve system performance by 29.7% over an aggressive baseline.
resistive RAM, resource allocation
C. Wang, D. Feng, J. Liu, W. Tong, B. Wu and Y. Zhang, "DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory," 2017 IEEE 35th International Conference on Computer Design (ICCD), Boston, MA, USA, 2018, pp. 281-288.