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2015 33rd IEEE International Conference on Computer Design (ICCD) (2015)
New York City, NY, USA
Oct. 18, 2015 to Oct. 21, 2015
ISBN: 978-1-4673-7165-0
pp: 419-422
Ji Wu , National Laboratory for Parallel and Distributed Processing, School of Computer National University of Defense Technology, Changsha, China
Dezun Dong , National Laboratory for Parallel and Distributed Processing, School of Computer National University of Defense Technology, Changsha, China
Xiangke Liao , National Laboratory for Parallel and Distributed Processing, School of Computer National University of Defense Technology, Changsha, China
Li Wang , National Laboratory for Parallel and Distributed Processing, School of Computer National University of Defense Technology, Changsha, China
ABSTRACT
Multi-NoC (multiple network-on-chip) has demonstrated its advantages in power gating for reducing leakage power. This work presents Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a performance-aware traffic allocation policy, Chameleon is able to achieve both high power efficiency and good performance at varying network utilization. Our experimental results show that Chameleon delivers an average of 3.39% higher performance than Catnap, the best in the literature. More importantly, Chameleon consumes an average of 17.16% less power than Catnap.
INDEX TERMS
Resource management, Routing, Algorithm design and analysis, Optimization, Logic gates, Computers, Power demand
CITATION

J. Wu, D. Dong, X. Liao and L. Wang, "Chameleon: Adaptive energy-efficient heterogeneous network-on-chip," 2015 33rd IEEE International Conference on Computer Design (ICCD), New York City, NY, USA, 2015, pp. 419-422.
doi:10.1109/ICCD.2015.7357138
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