2015 33rd IEEE International Conference on Computer Design (ICCD) (2015)
New York City, NY, USA
Oct. 18, 2015 to Oct. 21, 2015
Jude Angelo Ambrose , Canon Information Systems Research Australia (CiSRA), Sydney, Australia
Yusuke Yachide , Canon Information Systems Research Australia (CiSRA), Sydney, Australia
Kapil Batra , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Jorgen Peddersen , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Sri Parameswaran , Canon Information Systems Research Australia (CiSRA), Sydney, Australia
Pipeline of processors allow the execution of a sequential streaming program on multiple processors. However, partitioning sequential code for Multiprocessor Systems-on-Chips (MPSoCs), and then creating the MPSoC platform for the sequential code to execute, is a challenging problem. Parallelizing/pipelining statements within a control loop will improve the throughput of each iteration and the overall performance. Existing techniques, such as OpenMP, for parallelizing control loops is agnostic of the underlying MPSoC architecture, thus limiting the possibilities for further parallelisation. Previous techniques related to distribution of statements to MPSoCs considered homo geneous processors and not automated. In this paper, we propose a novel automated parallelization/ pipelining approach to synthesize a heterogeneous distributed pipelined MPSoC to improve the throughput of a loop (critical for streaming applications). An Integer Linear Programming (ILP)-based formulation to map statements to processor configurations is presented, in order to find the most suitable heterogeneous processor configurations for maximal throughput. Our approach complements state-of-the-art parallelization techniques, such as OpenMP, to further improve the performance of an application. A complete MPSoC platform, for the Tensilica framework, is automatically generated within minutes using our approach for the tested applications.
Program processors, Throughput, Pipelines, Optimization, Mathematical model, Indexes, Pluto
J. A. Ambrose, Y. Yachide, K. Batra, J. Peddersen and S. Parameswaran, "Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications," 2015 33rd IEEE International Conference on Computer Design (ICCD), New York City, NY, USA, 2015, pp. 216-223.