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2015 33rd IEEE International Conference on Computer Design (ICCD) (2015)
New York City, NY, USA
Oct. 18, 2015 to Oct. 21, 2015
ISBN: 978-1-4673-7165-0
pp: 46-53
Pouya Taatizadeh , Department of Electrical and Computer Engineering, McMaster University Hamilton, Ontario L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University Hamilton, Ontario L8S 4K1, Canada
ABSTRACT
The objective of post-silicon validation is to detect design errors on early silicon prototypes. Electrically-induced errors commonly manifest as bit-flips in the logic domain and they occur under unique operating conditions, which are often not-easily-repeatable. In order to shorten the long detection latencies from an error's manifestation until its observation (i.e. system crash), embedded assertion checkers can be employed. Nonetheless, relying on simulation-based experiments for selecting and assessing the usefulness of a subset of assertion checkers (to be committed to silicon) suffers from limitations associated with the slow simulation speed. To address this concern, in this paper we present a systematic method to automatically design emulation-based experiments that can aid the selection and assessment of the embedded assertion checkers. Our results indicate improvements of up to 10% on average for the coverage of flip-flops that are affected by bit-flips when compared to results obtained from simulation-based experiments.
INDEX TERMS
Hardware, Silicon, Flip-flops, Prototypes, Systematics, Manufacturing, Emulation
CITATION

P. Taatizadeh and N. Nicolici, "Emulation-based selection and assessment of assertion checkers for post-silicon validation," 2015 33rd IEEE International Conference on Computer Design (ICCD), New York City, NY, USA, 2015, pp. 46-53.
doi:10.1109/ICCD.2015.7357083
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