The Community for Technology Leaders
2014 32nd IEEE International Conference on Computer Design (ICCD) (2014)
Seoul, South Korea
Oct. 19, 2014 to Oct. 22, 2014
ISBN: 978-1-4799-6492-5
TABLE OF CONTENTS

Front cover (PDF)

pp. c1

Table of contents (PDF)

pp. II-IX

Message from the chairs (PDF)

Naehyuck Chang , Korea Advanced Institute of Science and Technology, Korea
Klaus Schneider , University of Kaiserslautern, Germany
Youngsoo Shin , Korea Advanced Institute of Science and Technology, Korea
Sule Ozev , Arizona State University, USA
pp. X

Program committee (PDF)

pp. XII-XIII

External reviewers (PDF)

pp. XIV-XV

Keynote presentations (PDF)

pp. XVI-XVIII

3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time (Abstract)

Ishan G Thakkar , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, U.S.A.
Sudeep Pasricha , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, U.S.A.
pp. 1-7

The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost (Abstract)

Lavanya Subramanian , Carnegie Mellon University, USA
Donghyuk Lee , Carnegie Mellon University, USA
Vivek Seshadri , Carnegie Mellon University, USA
Harsha Rastogi , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
pp. 8-15

Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory (Abstract)

Mengying Zhao , Department of Computer Science, City University of Hong Kong, Hong Kong
Liang Shi , College of Computer Science, Chongqing University, China
Chengmo Yang , Department of Electrical and Computer Engineering, University of Delaware Newark, US
Chun Jason Xue , Department of Computer Science, City University of Hong Kong, Hong Kong
pp. 16-21

ProactiveDRAM: A DRAM-initiated retention management scheme (Abstract)

Jue Wang , Pennsylvania State University, University Park, 16802 USA
Xiangyu Dong , Qualcomm Technologies, Inc., San Diego, California 92121 USA
Yuan Xie , University of California, Santa Barbara, 93106 USA
pp. 22-27

HAP: Hybrid-memory-Aware Partition in shared Last-Level Cache (Abstract)

Wei Wei , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Dejun Jiang , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Jin Xiong , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Mingyu Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 28-35

REEM: Failure/non-failure region estimation method for SRAM yield analysis (Abstract)

Manish Rana , Department Arquitectura de Computadors, Universitat Politecnica de Catalunya, Barcelona, Spain
Ramon Canal , Department Arquitectura de Computadors, Universitat Politecnica de Catalunya, Barcelona, Spain
pp. 36-41

Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA (Abstract)

Levent Aksoy , INESC-ID, Lisbon, Portugal
Paulo Flores , INESC-ID, Lisbon, Portugal
Jose Monteiro , INESC-ID, Lisbon, Portugal
pp. 42-47

A low-power accuracy-configurable floating point multiplier (Abstract)

Hang Zhang , Electrical and Computer Engineering, University of Virginia, Charlottesville, USA, 22904
Wei Zhang , Electrical and Computer Engineering, University of Virginia, Charlottesville, USA, 22904
John Lach , Electrical and Computer Engineering, University of Virginia, Charlottesville, USA, 22904
pp. 48-54

An area-efficient Ternary CAM design using floating gate transistors (Abstract)

Viacheslav V. Fedorov , ECEN Department, Texas A&M University, College Station, 77843, USA
Monther Abusultan , ECEN Department, Texas A&M University, College Station, 77843, USA
Sunil P. Khatri , ECEN Department, Texas A&M University, College Station, 77843, USA
pp. 55-60

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example (Abstract)

Andreas Steininger , Institute for Computer Engineering, Vienna University of Technology, Treitlstrasse 1-3, A-1040, Austria
Varadan S. Veeravalli , Institute for Computer Engineering, Vienna University of Technology, Treitlstrasse 1-3, A-1040, Austria
Dan Alexandrescu , IROC Technologies, 2 Square Roger Genin, 5th floor, 38000 Grenoble, France
Enrico Costenaro , IROC Technologies, 2 Square Roger Genin, 5th floor, 38000 Grenoble, France
Lorena Anghel , Laboratoire TIMA, 46, avenue Flix Viallet, 38031 Grenoble, France
pp. 61-67

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches (Abstract)

Shrikanth Ganapathy , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Ramon Canal , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Antonio Gonzalez , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Antonio Rubio , Department d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Barcelona, Spain
pp. 68-74

Multi-accelerator system development with the ShrinkFit acceleration framework (Abstract)

Michael J. Lyons , Harvard University, USA
Gu-Yeon Wei , Harvard University, USA
David Brooks , Harvard University, USA
pp. 75-82

Ternary cache: Three-valued MLC STT-RAM caches (Abstract)

Seokin Hong , Department of Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Jongmin Lee , Department of Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Soontae Kim , Department of Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea
pp. 83-89

Timing error masking by exploiting operand value locality in SIMD architecture (Abstract)

Jaehyeong Sim , Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea
Jun-Seok Park , Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea
Seungwook Paek , Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea
Lee-Sup Kim , Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea
pp. 90-96

Accurate prediction of detailed routing congestion using supervised data learning (Abstract)

Zhongdong Qi , Computer Science Department, Tsinghua University, Beijing, China
Yici Cai , Computer Science Department, Tsinghua University, Beijing, China
Qiang Zhou , Computer Science Department, Tsinghua University, Beijing, China
pp. 97-103

SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache (Abstract)

Pritam Majumder , PACE Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai-600036, India
Venkata Kalyan T , PACE Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai-600036, India
Madhu Mutyam , PACE Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai-600036, India
pp. 104-109

ReMAP: Reuse and memory access cost aware eviction policy for last level cache management (Abstract)

Akhil Arunkumar , School of Computing, Informatics, and Decision Systems Engineering, Arizona State University, Tempe, 85281, USA
Carole-Jean Wu , School of Computing, Informatics, and Decision Systems Engineering, Arizona State University, Tempe, 85281, USA
pp. 110-117

Increasing cache capacity via critical-words-only cache (Abstract)

Cheng-Chieh Huang , Institute of Computer Systems Architecture, University of Edinburgh, UK
Vijay Nagarajan , Institute of Computer Systems Architecture, University of Edinburgh, UK
pp. 125-132

Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration (Abstract)

Jianxing Wang , School of Computing, National University of Singapore, Republic of Singapore, 117417
Pooja Roy , School of Computing, National University of Singapore, Republic of Singapore, 117417
Weng-Fai Wong , School of Computing, National University of Singapore, Republic of Singapore, 117417
Xiuyuan Bi , Swanson School of Engineering, University of Pittsburgh, PA 15261, USA
Hai Li , Swanson School of Engineering, University of Pittsburgh, PA 15261, USA
pp. 133-138

ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap (Abstract)

Juan-Antonio Carballo , Broadcom Corporation, San Jose, CA 95134, USA
Wei-Ting Jonas Chan , ECE, UC San Diego, La Jolla, CA 92093, USA
Paolo A. Gargini , Stanford University, CA 94305, USA
Andrew B. Kahng , ECE, UC San Diego, La Jolla, CA 92093, USA
Siddhartha Nath , CSE Departments, UC San Diego, La Jolla, CA 92093, USA
pp. 139-146

More Moore landscape for system readiness - ITRS2.0 requirements (Abstract)

Mustafa Badaroglu , Qualcomm Technologies, Leuven, Belgium
Kwok Ng , SRC, Research Triangle Park, NC, USA
Mehdi Salmani , Purdue University, West Lafayette, IN, USA
SungGeun Kim , Intel Corporation, Hillsboro, OR, USA
Gerhard Klimeck , Purdue University, West Lafayette, IN, USA
Chorng-Ping Chang , Applied Materials, Santa Clara, CA, USA
Charles Cheung , NIST, Gaithersburg, MD, USA
Yuzo Fukuzaki , Sony Corporation, Atsugi, Japan
pp. 147-152

The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap (Abstract)

Wei-Ting Jonas Chan , ECE, UC San Diego, La Jolla, CA 92093, USA
Andrew B. Kahng , ECE, UC San Diego, La Jolla, CA 92093, USA
Siddhartha Nath , CSE Departments, UC San Diego, La Jolla, CA 92093, USA
Ichiro Yamamoto , Rohm Co., Ltd., Shinyokohama, Japan
pp. 153-160

Updates of the ITRS design cost and power models (Abstract)

Gary Smith , Gary Smith EDA, Santa Clara, CA 95055 USA
pp. 161-165

A lightweight and open-source framework for the lifetime estimation of multicore systems (Abstract)

Cristiana Bolchini , Dipartimento di Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Milan - Italy
Matteo Carminati , Dipartimento di Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Milan - Italy
Marco Gribaudo , Dipartimento di Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Milan - Italy
Antonio Miele , Dipartimento di Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Milan - Italy
pp. 166-172

Advanced modes in AES: Are they safe from power analysis based side channel attacks? (Abstract)

Darshana Jayasinghe , School of Computer Science and Engineering, University of New South Wales, Australia
Roshan Ragel , Department of Computer Engineering, University of Peradeniya, Sri Lanka
Jude Angelo Ambrose , School of Computer Science and Engineering, University of New South Wales, Australia
Aleksandar Ignjatovic , School of Computer Science and Engineering, University of New South Wales, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Australia
pp. 173-180

Built-in self-test for interposer-based 2.5D ICs (Abstract)

Ran Wang , ECE Dept., Duke University, Durham, NC, USA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, USA
Sudipta Bhawmik , Qualcomm Inc. Bridgewater, NJ, USA
pp. 181-188

An optimized diagnostic procedure for pre-bond TSV defects (Abstract)

Bei Zhang , Department of Electrical and Computer Engineering, Auburn University, AL 36849, USA
Vishwani D. Agrawal , Department of Electrical and Computer Engineering, Auburn University, AL 36849, USA
pp. 189-194

Equivalence verification for NULL Convention Logic (NCL) circuits (Abstract)

Vidura M. Wijayasekara , Department of Electrical and Computer Engineering, North Dakota State University, Fargo 58104, USA
Sudarshan K. Srinivasan , Department of Electrical and Computer Engineering, North Dakota State University, Fargo 58104, USA
Scott C. Smith , Department of Electrical and Computer Engineering, North Dakota State University, Fargo 58104, USA
pp. 195-201

Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems (Abstract)

Congming Gao , College of Computer Science, Chongqing University, China
Liang Shi , College of Computer Science, Chongqing University, China
Kaijie Wu , College of Computer Science, Chongqing University, China
Chun Jason Xue , Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong
Edwin H.-M. Sha , College of Computer Science, Chongqing University, China
pp. 202-207

Write-aware random page initialization for non-volatile memory systems (Abstract)

Fei Xia , SKL Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Dejun Jiang , SKL Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Jin Xiong , SKL Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Ninghui Sun , SKL Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 208-215

Loose-Ordering Consistency for persistent memory (Abstract)

Youyou Lu , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Jiwu Shu , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Long Sun , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Onur Mutlu , Computer Architecture Laboratory, Carnegie Mellon University, Pittsburgh, PA, USA
pp. 216-223

Design space exploration of an NVM-based memory hierarchy (Abstract)

Seungjae Baek , Department of Computer Science, Dankook University, Korea
Daeyeon Son , Department of Computer Science, Dankook University, Korea
Dongwoo Kang , Department of Computer Science, Dankook University, Korea
Jongmoo Choi , Department of Computer Science, Dankook University, Korea
Sangyeun Cho , Memory Division, Samsung Electronics, Korea
pp. 224-229

Timing characterization of clock buffers for clock tree synthesis (Abstract)

Can Sitik , Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA
Scott Lerner , Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA
Baris Taskin , Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA
pp. 230-236

Improving power delivery network design by practical methodologies (Abstract)

Chia-Chi Huang , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chang-Tzu Lin , Information and Communication Research Laboratory, Industrial Technology Research Institute, Taiwan
Wei-Syun Liao , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chieh-Jui Lee , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Hung-Ming Chen , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chia-Hsin Lee , Information and Communication Research Laboratory, Industrial Technology Research Institute, Taiwan
Ding-Ming Kwai , Information and Communication Research Laboratory, Industrial Technology Research Institute, Taiwan
pp. 237-242

Chip clustering with mutual information on multiple clock tests and its application to yield tuning (Abstract)

Jiun-Yi Chiang , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013
Jun-Hua Kuo , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013
Ting-Shuo Hsu , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013
Jing-Jia Liou , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013
pp. 243-248

Simultaneous EUV flare- and CMP-aware placement (Abstract)

Chi-Yuan Liu , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 249-255

Modeling and analysis of Phase Change Materials for efficient thermal management (Abstract)

Fulya Kaplan , ECE Department, Boston University, MA, USA
Charlie De Vivero , ECE Department, Boston University, MA, USA
Samuel Howes , ECE Department, Boston University, MA, USA
Manish Arora , Advanced Micro Devices, Inc., Boxborough, MA, USA
Houman Homayoun , ECE Department, George Mason University, Fairfax, VA, USA
Wayne Burleson , Advanced Micro Devices, Inc., Boxborough, MA, USA
Dean Tullsen , CSE Department, University of California, San Diego, USA
Ayse K. Coskun , ECE Department, Boston University, MA, USA
pp. 256-263

Improving multilevel PCM reliability through age-aware reading and writing strategies (Abstract)

Chen Liu , Department of Electrical and Computer Engineering, University of Delaware, 140 Evans Hall, Newark, 19716, USA
Chengmo Yang , Department of Electrical and Computer Engineering, University of Delaware, 140 Evans Hall, Newark, 19716, USA
pp. 264-269

BarTLB: Barren page resistant TLB for managed runtime languages (Abstract)

Xin Tong , University of Toronto, Canada
Andreas Moshovos , University of Toronto, Canada
pp. 270-277

Dynamic associative caches: Reducing dynamic energy of first level caches (Abstract)

Karthikeyan Dayalan , State University of New York at Binghamton, USA
Meltem Ozsoy , State University of New York at Binghamton, USA
Dmitry Ponomarev , State University of New York at Binghamton, USA
pp. 118-124

A Thread-Aware Adaptive Data Prefetcher (Abstract)

Jiyang Yu , Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China
Peng Liu , Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China
pp. 278-285

Dynamic front-end sharing in graphics processing units (Abstract)

Tao Zhang , Department of Computer Science and Engineering, Shanghai Jiao Tong University, China, 200240
Xiaoyao Liang , Department of Computer Science and Engineering, Shanghai Jiao Tong University, China, 200240
pp. 286-291

Leveraging dynamic slicing to enhance indirect branch prediction (Abstract)

Walid J. Ghandour , Computer Engineering Department, Fahad Bin Sultan University, Tabuk, Saudi Arabia
Nadine J. Ghandour , Mathematics Department, Lebanese University, Beirut, Lebanon
pp. 292-299

DFM is dead - Long live DFM (Abstract)

Robert Aitken , ARM R&D, San Jose, CA, USA
David Pietromonaco , ARM R&D, San Jose, CA, USA
Brian Cline , ARM R&D, Austin, TX, USA
pp. 300-307

Pattern-restricted design at 10nm and beyond (Abstract)

Rani S. Ghaida , GLOBALFOUNDRIES, Technology Development Division, Santa Clara, CA, USA
Yasmine Badr , University of California, Los Angeles, Electrical Engineering Department, CA, USA
Puneet Gupta , University of California, Los Angeles, Electrical Engineering Department, CA, USA
pp. 308-310

Improved signoff methodology with tightened BEOL corners (Abstract)

Tuck-Boon Chan , ECE Departments, UC San Diego, La Jolla, CA 92093, USA
Sorin Dobre , Qualcomm Technologies, Inc., San Diego, CA 92121, USA
Andrew B. Kahng , CSE Departments, UC San Diego, La Jolla, CA 92093, USA
pp. 311-316

Accelerating divergent applications on SIMD architectures using neural networks (Abstract)

Beayna Grigorian , Computer Science Department, University of California, Los Angeles (UCLA), USA
Glenn Reinman , Computer Science Department, University of California, Los Angeles (UCLA), USA
pp. 317-323

Power-capped DVFS and thread allocation with ANN models on modern NUMA systems (Abstract)

Satoshi Imamura , Graduate School and Faculty of Information Science and Electrical Engineering, Kyushu University, Fukuoka, Japan
Hiroshi Sasaki , Department of Computer Science, Columbia University, New York, USA
Koji Inoue , Graduate School and Faculty of Information Science and Electrical Engineering, Kyushu University, Fukuoka, Japan
Dimitrios S. Nikolopoulos , School of Electronics, Electrical Engineering and Computer Science, Queen's University Belfast, UK
pp. 324-331

QoS management on heterogeneous architecture for parallel applications (Abstract)

Ying Zhang , Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, USA
Li Zhao , Intel Labs, Intel Corporation, Hillsboro, OR, USA
Ramesh Illikkal , Intel Labs, Intel Corporation, Hillsboro, OR, USA
Ravi Iyer , Intel Labs, Intel Corporation, Hillsboro, OR, USA
Andrew Herdrich , Intel Labs, Intel Corporation, Hillsboro, OR, USA
Lu Peng , Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, USA
pp. 332-339

Software pipelining of dataflow programs with dynamic constructs on multi-core processor (Abstract)

Yogesh Murarka , Samsung R&D Institute India - Bangalore, India
Pankaj Gode , Samsung R&D Institute India - Bangalore, India
Sirish Kumar Pasupuleti , Samsung R&D Institute India - Bangalore, India
Soma Kohli , Samsung R&D Institute India - Bangalore, India
pp. 340-347

Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes (Abstract)

Daming Zhang , Dept. of Electronic Engineering, Tsinghua University, Beijing, 100084, China
Shuangchen Li , Dept. of Electronic Engineering, Tsinghua University, Beijing, 100084, China
Ang Li , Dept. of Electronic Engineering, Tsinghua University, Beijing, 100084, China
Yongpan Liu , Dept. of Electronic Engineering, Tsinghua University, Beijing, 100084, China
X. Sharon Hu , Dept. of Computer Science and Engineering, University of Notre Dame, IN 46556, U.S.
Huazhong Yang , Dept. of Electronic Engineering, Tsinghua University, Beijing, 100084, China
pp. 348-354

Boolean circuit design using emerging tunneling devices (Abstract)

Behnam Sedighi , Dept. of Electrical Engineering, University of Notre Dame, IN 46556, USA
Joseph J. Nahas , Dept. of Electrical Engineering, University of Notre Dame, IN 46556, USA
Michael Niemier , Dept. of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
Xiaobo Sharon Hu , Dept. of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
pp. 355-360

Compact and accurate stochastic circuits with shared random number sources (Abstract)

Hideyuki Ichihara , School of Information Sciences, Hiroshima City University, Asaminami, Japan 7313194
Shota Ishii , School of Information Sciences, Hiroshima City University, Asaminami, Japan 7313194
Daiki Sunamori , School of Information Sciences, Hiroshima City University, Asaminami, Japan 7313194
Tsuyoshi Iwagaki , School of Information Sciences, Hiroshima City University, Asaminami, Japan 7313194
Tomoo Inoue , School of Information Sciences, Hiroshima City University, Asaminami, Japan 7313194
pp. 361-366

Analyzing and controlling accuracy in stochastic circuits (Abstract)

Te-Hsuan Chen , Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan, Ann Arbor, 48109, USA
John P. Hayes , Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan, Ann Arbor, 48109, USA
pp. 367-373

Low write-energy STT-MRAMs using FinFET-based access transistors (Abstract)

Alireza Shafaei , Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
Yanzhi Wang , Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
Massoud Pedram , Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
pp. 374-379

Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology (Abstract)

Qing Xie , Department of Electrical Engineering, University of Southern California, Los Angeles, United States
Yanzhi Wang , Department of Electrical Engineering, University of Southern California, Los Angeles, United States
Shuang Chen , Department of Electrical Engineering, University of Southern California, Los Angeles, United States
Massoud Pedram , Department of Electrical Engineering, University of Southern California, Los Angeles, United States
pp. 380-385

The heterogeneous block architecture (Abstract)

Chris Fallin , Carnegie Mellon University, USA
Chris Wilkerson , Intel Corporation, USA
Onur Mutlu , Carnegie Mellon University, USA
pp. 386-393

An asynchronous Network-on-Chip router with low standby power (Abstract)

Amr Elshennawy , Department of ECE, Texas A&M University, College Station 77843, USA
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station 77843, USA
pp. 394-399

NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores (Abstract)

Xiang Pan , Department of Computer Science and Engineering, The Ohio State University, Columbus, USA
Radu Teodorescu , Department of Computer Science and Engineering, The Ohio State University, Columbus, USA
pp. 400-407

Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores (Abstract)

Elliott Forbes , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA
Niket K. Choudhary , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA
Brandon H. Dwiel , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA
Eric Rotenberg , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA
pp. 408-415

Energy efficiency improvement of renamed trace cache through the reduction of dependent path length (Abstract)

Ryota Shioya , Department of Electrical Engineering and Computer Science, Nagoya University, Aichi, Japan
Hideki Ando , Department of Electrical Engineering and Computer Science, Nagoya University, Aichi, Japan
pp. 416-423

Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips (Abstract)

Costas Iordanou , Department of Electrical Eng., Computer Eng. and Informatics, Cyprus University of Technology, Cyprus
Vassos Soteriou , Department of Electrical Eng., Computer Eng. and Informatics, Cyprus University of Technology, Cyprus
Konstantinos Aisopos , Microsoft Corporation, WA 98052, USA
pp. 424-431

An energy efficient column-major backend for FPGA SpMV accelerators (Abstract)

Yaman Umuroglu , Department of Computer and Information Science, Norwegian University of Science and Technology, Trondheim, Norway
Magnus Jahre , Department of Computer and Information Science, Norwegian University of Science and Technology, Trondheim, Norway
pp. 432-439

Fair share: Allocation of GPU resources for both performance and fairness (Abstract)

Paula Aguilera , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
Katherine Morrow , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
Nam Sung Kim , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
pp. 440-447

Dynamic variability management in mobile multicore processors under lifetime constraints (Abstract)

Pietro Mercati , UCSD, USA
Francesco Paterna , UCSD, USA
Andrea Bartolini , ETH Zurich, Switzerland
Luca Benini , ETH Zurich, Switzerland
pp. 448-455

Design space exploration of multiple loops on FPGAs using high level synthesis (Abstract)

Guanwen Zhong , School of Computing, National University of Singapore, Singapore
Vanchinathan Venkataramani , School of Computing, National University of Singapore, Singapore
Yun Liang , Center for Energy-Efficient Computing and Applications, School of EECS, Peking University, China
Tulika Mitra , School of Computing, National University of Singapore, Singapore
Smail Niar , LAMIH, University of Valenciennes, France
pp. 456-463

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping (Abstract)

Vinay B.Y. Kumar , Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India
Shovan Maity , Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India
Sachin B. Patkar , Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India
pp. 464-469

HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs (Abstract)

Yuchun Ma , Tsinghua University, China
Jinglan Liu , Beijing University of Posts and Telecommunications, China
Chao Zhang , Tsinghua University, China
Wayne Luk , Imperial College, UK
pp. 470-476

Power supply and consumption co-optimization of portable embedded systems with hybrid power supply (Abstract)

Xue Lin , Dept. Electrical Engineering, University of Southern California, Los Angeles, USA
Yanzhi Wang , Dept. Electrical Engineering, University of Southern California, Los Angeles, USA
Naehyuck Chang , Dept. Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea
Massoud Pedram , Dept. Electrical Engineering, University of Southern California, Los Angeles, USA
pp. 477-482

Automated generation of battery aging models from datasheets (Abstract)

Massimo Petricca , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Italy
Donghwa Shin , Yeungnam University, 280 Daehak-Ro, Gyeongsan, Gyeongbuk 712-749, Republic of Korea
Alberto Bocca , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Italy
Alberto Macii , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Italy
Enrico Macii , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Italy
Massimo Poncino , Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Italy
pp. 483-488

Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs (Abstract)

Stelios N. Neophytou , ECE Dept., University of Nicosia and KIOS Center for Intelligent Systems and Networks, Cyprus
Maria K. Michael , ECE Dept., University of Cyprus and KIOS Center for Intelligent Systems and Networks, Cyprus
pp. 489-492

Hybrid modeling attacks on current-based PUFs (Abstract)

Raghavan Kumar , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
Wayne Burleson , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
pp. 493-496

CoolBudget: Data center power budgeting with workload and cooling asymmetry awareness (Abstract)

Ozan Tuncer , ECE Department, Boston University, Boston, MA 02215, USA
Kalyan Vaidyanathan , Oracle Physical Sciences Research Center, San Diego, CA 92121, USA
Kenny Gross , Oracle Physical Sciences Research Center, San Diego, CA 92121, USA
Ayse K. Coskun , ECE Department, Boston University, Boston, MA 02215, USA
pp. 497-500

Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems (Abstract)

Siddharth Advani , Pennsylvania State University, USA
Nandhini Chandramoorthy , Pennsylvania State University, USA
Karthik Swaminathan , Pennsylvania State University, USA
Kevin Irick , SiliconScapes LLC., USA
Yong Cheol Peter Cho , ETRI, South Korea
Jack Sampson , Pennsylvania State University, USA
Vijaykrishnan Narayanan , Pennsylvania State University, USA
pp. 501-504

Exploiting natural redundancy in visual information (Abstract)

Chris S. Lee , Pennsylvania State University, USA
Kevin M. Irick , SiliconScapes, LLC, PA, USA
Jack Sampson , Pennsylvania State University, USA
Chuanjun Zhang , Intel, PA, USA
Vijaykrishnan Narayanan , Pennsylvania State University, USA
pp. 505-508

Dark silicon aware power management for manycore systems under dynamic workloads (Abstract)

Mohammad-Hashem Haghbayan , Department of Information Technology, University of Turku, Finland
Amir-Mohammad Rahmani , Department of Information Technology, University of Turku, Finland
Awet Yemane Weldezion , School of ICT, KTH Royal Institute of Technology, Stockholm, Sweden
Pasi Liljeberg , Department of Information Technology, University of Turku, Finland
Juha Plosila , Department of Information Technology, University of Turku, Finland
Axel Jantsch , School of ICT, KTH Royal Institute of Technology, Stockholm, Sweden
Hannu Tenhunen , Department of Information Technology, University of Turku, Finland
pp. 509-512

Cache design for mixed criticality real-time systems (Abstract)

N G Chetan Kumar , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
Sudhanshu Vyas , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
Ron K. Cytron , Department of Computer Science and Engineering, Washington University, St. Louis, MO, USA
Christopher D. Gill , Department of Computer Science and Engineering, Washington University, St. Louis, MO, USA
Joseph Zambreno , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
Phillip H. Jones , Department of Electrical and Computer Engineering, Iowa State University, Ames, USA
pp. 513-516

Static thread mapping for NoCs via binary instrumentation traces (Abstract)

Giordano Salvador , University of Pennsylvania, Philadelphia, USA
Siddharth Nilakantan , Drexel University, Philadelphia, Pennsylvania, USA
Baris Taskin , Drexel University, Philadelphia, Pennsylvania, USA
Mark Hempstead , Drexel University, Philadelphia, Pennsylvania, USA
Ankit More , Intel Corporation, Portland, Oregon, USA
pp. 517-520

ScalaHDL: Express and test hardware designs in a Scala DSL (Abstract)

Yao Li , Shanghai Jiao Tong University, China
Antonio Roldao Lopes , Morgan Stanley, London, United Kingdom
Zhouyun Xu , Morgan Stanley, Shanghai, China
Zhengwei Qi , Shanghai Jiao Tong University, China
Haibing Guan , Shanghai Jiao Tong University, China
pp. 521-524

PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs (Abstract)

Nishit Kapadia , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, U.S.A.
Sudeep Pasricha , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, U.S.A.
pp. 525-528

Author index (PDF)

pp. 529-532
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