The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (2012)
Montreal, QC, Canada Canada
Sept. 30, 2012 to Oct. 3, 2012
ISSN: 1063-6404
ISBN: 978-1-4673-3051-0
TABLE OF CONTENTS
Papers

Cloud computing: Virtualization and resiliency for data center computing (Abstract)

Valentina Salapura , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
pp. 1-2

FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper (Abstract)

Josep Torrellas , Department of Computer Science, University of Illinois
pp. 3-4

FlexRAM: Toward an advanced Intelligent Memory system (Abstract)

Josep Torrellas , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
Vinh Lam , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
Zhenzhou Ge , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
Seung-Moon Yoo , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
Diana Keen , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
Wei Huang , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
Yi Kang , Department of Computer Science, University of Illinois at Urbana-Champaign, IL 61801
pp. 5-14

Retrospective on “Power-Sensitive Multithreaded Architecture” (Abstract)

George Z. N. Cai , Intel Corporation, Hillsboro, OR
John S. Seng , Computer Science Department, California Polytechnic State, University, San Luis Obispo, San Luis Obispo, CA
Dean M. Tullsen , Dept. of Computer Science and Engineering, University of California, San Diego La Jolla, CA
pp. 15-16

Power-sensitive multithreaded architecture (Abstract)

Oeorge Z. N. Cai , Intel Corporation, RA2-401, 2501 N.W. 229th Ave, Hillsboro, OR 97124
John S. Seng , Dept. of Computer Science and Engineering, University of California, San Diego, La Jolla, CA 92093-0114
Dean M. Tullsen , Dept. of Computer Science and Engineering, University of California, San Diego, La Jolla, CA 92093-0114
pp. 17-24

Architectural impact of secure socket layer on Internet servers: A retrospect (Abstract)

Krishna Kant , Intel Corporation, Hillsboro, Oregon
Ravishankar Iyer , Intel Corporation, Hillsboro, Oregon
Prasant Mohapatra , University of California, Davis, CA
pp. 25-26

Architectural impact of secure socket layer on Internet servers (Abstract)

Krishna Kant , Server Architecture Lab, Intel Corporation, Beaverton, OR
Ravishankar Iyer , Server Architecture Lab, Intel Corporation, Beaverton, OR
Prasant Mohapatra , Dept. of Computer Science and Engineering, Michigan state University, East Lansing, MI
pp. 27-34

Exploiting microarchitectural redundancy for defect tolerance (Abstract)

Doug Burger , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin
Premkishore Shivakumar , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin
Stephen W. Keckler , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin
Charles R. Moore , Computer Architecture and Technology Laboratory, Department of Computer Sciences, The University of Texas at Austin
pp. 35-42

A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip (Abstract)

Davide Bertozzi , Engineering Department, University of Ferrara, Ferrara, Italy
Luca Benini , DEIS, University of Bologna, Bologna, Italy
pp. 43-44

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs (Abstract)

Luca Benini , University of Bologna, DEIS, Viale Risorgimento, 2 Bologna (Italy)
Luca Giovannini , University of Bologna, DEIS, Viale Risorgimento, 2 Bologna (Italy)
Davide Bertozzi , University of Bologna, DEIS, Viale Risorgimento, 2 Bologna (Italy)
Matteo Dall'Osso , University of Bologna, DEIS, Viale Risorgimento, 2 Bologna (Italy)
Gianluca Biccari , University of Bologna, DEIS, Viale Risorgimento, 2 Bologna (Italy)
pp. 45-48

Task model suitable for dynamic load balancing of real-time applications in NoC-based MPSoCs (Abstract)

Oliver Longhi , Faculty of Informatics - PUCRS - Av. Ipiranga 6681, Porto Alegre, Brazil
Fabiano Hessel , Faculty of Informatics - PUCRS - Av. Ipiranga 6681, Porto Alegre, Brazil
Felipe Gohring de Magalhaes , Faculty of Informatics - PUCRS - Av. Ipiranga 6681, Porto Alegre, Brazil
Sergio Johann Filho , Faculty of Informatics - PUCRS - Av. Ipiranga 6681, Porto Alegre, Brazil
Alexandra Aguiar , Faculty of Informatics - PUCRS - Av. Ipiranga 6681, Porto Alegre, Brazil
pp. 49-54

BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip (Abstract)

Jose-Angel Gregorio , University of Cantabria, Santander, Spain
Pablo Abad , University of Cantabria, Santander, Spain
Pablo Prieto , University of Cantabria, Santander, Spain
Valentin Puente , University of Cantabria, Santander, Spain
pp. 55-60

Exploiting multi-level scratchpad memories for time-predictable multicore computing (Abstract)

Yu Liu , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL, USA 62901
Wei Zhang , Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA, USA 23284
pp. 61-66

SECRET: Selective error correction for refresh energy reduction in DRAMs (Abstract)

Michael Wang , Macronix International Co., Ltd
Chia-Lin Yang , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
Chung-Hsiang Lin , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
De-Yu Shen , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
Yi-Jung Chen , Department of Computer Science and Information Engineering, National Chi Nan University, Nantou, Taiwan
pp. 67-74

DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC (Abstract)

Jian Li , IBM Research - Austin, 11501 Burnet Road Austin, TX 78758, USA
Yi Wang , The Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA 70503, USA
Dan Zhao , The Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA 70503, USA
pp. 75-80

Reinforcement learning based dynamic power management with a hybrid power supply (Abstract)

Massoud Pedram , University of Southern California, Department of Electrical Engineering, Los Angeles, CA USA
Yanzhi Wang , University of Southern California, Department of Electrical Engineering, Los Angeles, CA USA
Siyu Yue , University of Southern California, Department of Electrical Engineering, Los Angeles, CA USA
Di Zhu , University of Southern California, Department of Electrical Engineering, Los Angeles, CA USA
pp. 81-86

A PRET microarchitecture implementation with repeatable timing and competitive performance (Abstract)

Edward A. Lee , University of California, Berkeley, CA, USA
Isaac Liu , University of California, Berkeley, CA, USA
Jan Reineke , Saarland University, Germany
David Broman , Linköping University, Sweden
Michael Zimmer , University of California, Berkeley, CA, USA
pp. 87-93

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime (Abstract)

Ken Mai , DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Osman S. Unsal , Barcelona Supercomputing Center, C/Jordi Girona 29, Barcelona, Spain
Erich F. Haratsch , LSI Corporation, 1110 American Parkway NE, Allentown, PA
Adrian Cristal , Barcelona Supercomputing Center, C/Jordi Girona 29, Barcelona, Spain
Yu Cai , DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Gulay Yalcin , Barcelona Supercomputing Center, C/Jordi Girona 29, Barcelona, Spain
Onur Mutlu , DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 94-101

A high-performance, low-overhead microarchitecture for secure program execution (Abstract)

Arun K. Kanuparthi , Polytechnic Institute of NYU, Brooklyn, NY 11201
Ramesh Karri , Polytechnic Institute of NYU, Brooklyn, NY 11201
Gaston Ormazabal , Columbia University, New York, NY 10027
Sateesh K. Addepalli , Cisco Systems, San Jose, CA 95134
pp. 102-107

Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints (Abstract)

Mohammad Ghasemazar , University of Southern California, Department of Electrical Engineering, Los Angeles, CA 90089 U.S.A.
Hadi Goudarzi , University of Southern California, Department of Electrical Engineering, Los Angeles, CA 90089 U.S.A.
Massoud Pedram , University of Southern California, Department of Electrical Engineering, Los Angeles, CA 90089 U.S.A.
pp. 108-114

Hierarchical modeling of Phase Change memory for reliable design (Abstract)

Chaitali Chakrabarti , School of ECEE, Arizona State University, Tempe, AZ 85287, USA
Yu Cao , School of ECEE, Arizona State University, Tempe, AZ 85287, USA
Chengen Yang , School of ECEE, Arizona State University, Tempe, AZ 85287, USA
Ketul B. Sutaria , School of ECEE, Arizona State University, Tempe, AZ 85287, USA
Zihan Xu , School of ECEE, Arizona State University, Tempe, AZ 85287, USA
pp. 115-120

Clock mesh synthesis method using the Earth Mover's Distance under transformations (Abstract)

Baris Taskin , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104
Ying Teng , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104
pp. 121-126

Malicious key emission via hardware Trojan against encryption system (Abstract)

Jeremy Dubeuf , Grenoble INP-Esisar, Valence, France
Yves Clauzel , Grenoble INP-Esisar, Valence, France
Maurin Augagneur , Grenoble INP-Esisar, Valence, France
David Hely , Grenoble INP, LCIS, Valence, France
pp. 127-130

Exposing vulnerabilities of untrusted computing platforms (Abstract)

Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas
Yier Jin , Department of Electrical Engineering, Yale University
Michail Maniatakos , Department of Electrical Engineering, Yale University
pp. 131-134

A physical unclonable function based on setup time violation (Abstract)

Jeremy Dubeuf , Grenoble INP-Esisar, Valence, France
Yves Clauzel , Grenoble INP-Esisar, Valence, France
David Hely , Grenoble INP, LCIS, Valence, France
Maurin Augagneur , Grenoble INP-Esisar, Valence, France
pp. 135-138

Design and evaluation of a delay-based FPGA Physically Unclonable Function (Abstract)

Phillip Jones , Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Joseph Zambreno , Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Christopher Sabotta , Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Michael Patterson , Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Sudhanshu Vyas , Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Aaron Mills , Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
pp. 143-146

Adaptable intrusion detection using partial runtime reconfiguration (Abstract)

Elaheh Bozorgzadeh , Computer Science Department, University of California, Irvine, Irvine, USA
Mehryar Rahmatian , Computer Science Department, University of California, Irvine, Irvine, USA
Hessam Kooti , Computer Science Department, University of California, Irvine, Irvine, USA
Ian G. Harris , Computer Science Department, University of California, Irvine, Irvine, USA
pp. 147-152

Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening (Abstract)

Subramanian Poothamkurissi Swaminathan , Department of ECE, Texas A&M University, College Station TX 77843
Pey-Chang Kent Lin , Department of ECE, Texas A&M University, College Station TX 77843
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843
pp. 153-158

Maximizing crosstalk-induced slowdown during path delay test (Abstract)

Dibakar Gope , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin
D. M. H. Walker , Department of Computer Science Texas A&M University College Station, Texas
pp. 159-166

Embedded way prediction for last-level caches (Abstract)

Thomas F. Wenisch , Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Faissal M. Sleiman , Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Ronald G. Dreslinski , Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
pp. 167-174

Thermal characterization of cloud workloads on a power-efficient server-on-chip (Abstract)

Yiannakis Sazeides , University of Cyprus
Damien Hardy , University of Cyprus
Andreas Panteli , University of Cyprus
Andreas Prodromou , University of Cyprus
Chrysostomos Nicopoulos , University of Cyprus
Emre Ozer , ARM
pp. 175-182

Design methodology for sample preparation on digital microfluidic biochips (Abstract)

Krishnendu Chakrabarty , Dept. of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Yi-Ling Hsieh , Dept. of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Tsung-Yi Ho , Dept. of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
pp. 189-194

An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT (Abstract)

Ayan Mandal , Department of ECE, Texas A&M University, College Station TX 77843
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843
Rajeev Kumar , Department of ECE, Texas A&M University, College Station TX 77843
pp. 195-200

Multi-voltage domain clock mesh design (Abstract)

Baris Taskin , Electrical and Computer Engineering, Drexel University, Philadelphia, PA, 19104 USA
Can Sitik , Electrical and Computer Engineering, Drexel University, Philadelphia, PA, 19104 USA
pp. 201-206

Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures (Abstract)

Juan Manuel Castillo , Institute of Thermodynamics and Thermal Process Engineering, University of Stuttgart, Pfaffenwaldring 9, D-70569, Germany
Joachim Gross , Institute of Thermodynamics and Thermal Process Engineering, University of Stuttgart, Pfaffenwaldring 9, D-70569, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Claus Braun , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Stefan Holst , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569, Germany
pp. 207-212

Understanding variance propagation in stochastic computing systems (Abstract)

Hua Dang , School of Information and Electronics, Beijing Institute of Technology, Beijing, China 100081
Chengguang Ma , School of Information and Electronics, Beijing Institute of Technology, Beijing, China 100081
Shunan Zhong , School of Information and Electronics, Beijing Institute of Technology, Beijing, China 100081
pp. 213-218

Parametric throughput analysis of scenario-aware dataflow graphs (Abstract)

Henk Corporaal , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Twan Basten , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Marc Geilen , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Morteza Damavandpeyma , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Sander Stuijk , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 219-226

A polynomial time flow for implementing free-choice Petri-nets (Abstract)

Christos P. Sotiriou , FORTH-ICS, Crete, Greece and University of Crete, Greece
Peter A. Beerel , Department of Electrical Engineering, University of Southern California, USA
Pavlos M. Mattheakis , FORTH-ICS, Crete, Greece and University of Crete, Greece
pp. 227-234

A flexible structure of standard cell and its optimization method for near-threshold voltage operation (Abstract)

Hidetoshi Onodera , Graduate School of Informatics, Kyoto Univesity, Yoshida-honmachi, Sakyo, Kyoto, 606-8501, Japan
Shinichi Nishizawa , Graduate School of Informatics, Kyoto Univesity, Yoshida-honmachi, Sakyo, Kyoto, 606-8501, Japan
Tohru Ishihara , Graduate School of Informatics, Kyoto Univesity, Yoshida-honmachi, Sakyo, Kyoto, 606-8501, Japan
pp. 235-240

HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips (Abstract)

Vassos Soteriou , Department of EECEI, Cyprus University of Technology
Theocharis Theocharides , KIOS Research Center, Department of ECE, University of Cyprus
Elena Kakoulli , Department of EECEI, Cyprus University of Technology
pp. 249-255

Phase-based passive stereovision systems dedicated to cortical visual stimulators (Abstract)

Firas Hawi , Polystim Neurotechnologies Laboratory, Departement of Electrical Engineering, Polytechnique Montreal., Montreal, Canada
Mohamad Sawan , Polystim Neurotechnologies Laboratory, Departement of Electrical Engineering, Polytechnique Montreal., Montreal, Canada
pp. 256-262

Interface design for synthesized structural hybrid microarchitectural simulators (Abstract)

David A. Penry , Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA
Zhuo Ruan , Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA
pp. 263-270

A comparative study of wearout mechanisms in state-of-art microprocessors (Abstract)

Linda Milor , School of Electrical and Comptuer Engineering, Georgia Institute of Technology, Atlanta, GA USA
Fahad Ahmed , School of Electrical and Comptuer Engineering, Georgia Institute of Technology, Atlanta, GA USA
Chang-Chih Chen , School of Electrical and Comptuer Engineering, Georgia Institute of Technology, Atlanta, GA USA
pp. 271-276

Mamba: A scalable communication centric multi-threaded processor architecture (Abstract)

Gregory A. Chadwick , Computer Laboratory, University of Cambridge, UK
Simon W. Moore , Computer Laboratory, University of Cambridge, UK
pp. 277-283

Dynamic phase-based tuning for embedded systems using phase distance mapping (Abstract)

Arslan Munir , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Ann Gordon-Ross , Center for High Performance Reconfigurable, Computing (CHREC) at the University of Florida
Tosiron Adegbija , Department of Electrical and Computer Engineering, University of Florida, Gainesville, Florida, USA
pp. 284-290

SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency (Abstract)

Jiangfang Yi , Microprocessor Research & Development Center, Peking Universityy, Beijing, China 100871
Keyi Wang , Microprocessor Research & Development Center, Peking Universityy, Beijing, China 100871
Xiaoyin Wang , Microprocessor Research & Development Center, Peking Universityy, Beijing, China 100871
Zhenhao Zhang , Microprocessor Research & Development Center, Peking Universityy, Beijing, China 100871
Dong Tong , Microprocessor Research & Development Center, Peking Universityy, Beijing, China 100871
pp. 291-296

Analyzing the optimal ratio of SRAM banks in hybrid caches (Abstract)

Jose Duato , Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain
Pedro Lopez , Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain
Salvador Petit , Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain
Alejandro Valero , Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain
Julio Sahuquillo , Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain
pp. 297-302

A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic (Abstract)

Peng Li , Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA
Weikang Qian , University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai, China
David J. Lilja , Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA
pp. 303-308

Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs (Abstract)

Ramon Canal , Dept. of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain
Zoran Jaksic , Dept. of Computer Architecture, Universitat Politecnica de Catalunya, Barcelona, Spain
pp. 309-314

Fast error aware model for arithmetic and logic circuits (Abstract)

Amin Khajeh , Intel Labs, Hillsboro, Oregon, USA
Ahmed M. Eltawil , Electrical Engineering and Computer Science Department, University of California Irvine, Irvine, CA, USA
Fadi J. Kurdahi , Electrical Engineering and Computer Science Department, University of California Irvine, Irvine, CA, USA
Samy Zaynoun , Electrical Engineering and Computer Science Department, University of California Irvine, Irvine, CA, USA
Muhammad S. Khairy , Electrical Engineering and Computer Science Department, University of California Irvine, Irvine, CA, USA
pp. 322-328

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications (Abstract)

Steven M. Nowick , Department of Computer Science, Columbia University in the City of New York, New York, NY, 10027, USA
Christos Vezyrtzis , Department of Electrical Engineering, Columbia University in the City of New York, New York, NY, 10027, USA
Yannis Tsividis , Department of Electrical Engineering, Columbia University in the City of New York, New York, NY, 10027, USA
pp. 329-336

Row buffer locality aware caching policies for hybrid memories (Abstract)

Onur Mutlu , Carnegie Mellon University
Rachata Ausavarungnirun , Carnegie Mellon University
Rachael A. Harding , Carnegie Mellon University
Justin Meza , Carnegie Mellon University
HanBin Yoon , Carnegie Mellon University
pp. 337-344

Mitigating NBTI in the physical register file through stress prediction (Abstract)

Sanghamitra Roy , BRIDGE Lab, Electrical and Computer Engineering, Utah State University
Koushik Chakraborty , BRIDGE Lab, Electrical and Computer Engineering, Utah State University
Saurabh Kothawade , Qualcomm Inc., San Diego, California
Dean Michael Ancajas , BRIDGE Lab, Electrical and Computer Engineering, Utah State University
pp. 345-351

An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits (Abstract)

Saeed Safari , School of Electrical and Computer Engineering, University of Tehran, Iran
Ali Afzali-Kusha , School of Electrical and Computer Engineering, University of Tehran, Iran
Massoud Pedram , Department of Electrical Engineering - Systems, University of Southern California, USA
Mehdi Kamal , School of Electrical and Computer Engineering, University of Tehran, Iran
Qing Xie , Department of Electrical Engineering - Systems, University of Southern California, USA
pp. 352-357

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications (Abstract)

C. Vezyrtzis , Dept. of Electr. Eng., Columbia Univ. in the City of New York, New York, NY, USA
Y. Tsividis , Dept. of Electr. Eng., Columbia Univ. in the City of New York, New York, NY, USA
S. M. Nowick , Dept. of Comput. Sci., Columbia Univ. in the City of New York, New York, NY, USA
pp. 329-336
Papers

CoNA: Dynamic application mapping for congestion reduction in many-core systems (Abstract)

Juha Plosila , Department of Information Technology, University of Turku, Turku, Finland
Pasi Liljeberg , Department of Information Technology, University of Turku, Turku, Finland
Masoud Daneshtalab , Department of Information Technology, University of Turku, Turku, Finland
Mohamamd Fattah , Department of Information Technology, University of Turku, Turku, Finland
Marco Ramirez , Department of Information Technology, University of Turku, Turku, Finland
pp. 364-370

DIPLOMA: Consistent and coherent shared memory over mobile phones (Abstract)

HaoQi Li , M.I.T. Computer Science & Artificial Intelligence Laboratory, Cambridge, MA, USA
Li-Shiuan Peh , M.I.T. Computer Science & Artificial Intelligence Laboratory, Cambridge, MA, USA
Niket Agarwal , Google Inc., Mountain View, CA, USA
Jason Gao , M.I.T. Computer Science & Artificial Intelligence Laboratory, Cambridge, MA, USA
Anirudh Sivaraman , M.I.T. Computer Science & Artificial Intelligence Laboratory, Cambridge, MA, USA
pp. 371-378

Aurora: A thermally resilient photonic network-on-chip architecture (Abstract)

Xin Fu , University of Kansas, Lawrence, USA
Tao Li , University of Florida, Gainesville, USA
Wangyuan Zhang , NetApp, Pittsburgh, USA
Amer Qouneh , University of Florida, Gainesville, USA
Zhongqi Li , University of Florida, Gainesville, USA
Madhura Joshi , Infinera, Sunnyvale, USA
pp. 379-386

Improving inclusive cache performance with two-level eviction priority (Abstract)

Junlin Lu , Microprocessor Research and Development Center, Peking University, Beijing, China
Xu Cheng , Microprocessor Research and Development Center, Peking University, Beijing, China
Zichao Xie , Microprocessor Research and Development Center, Peking University, Beijing, China
Lingda Li , Microprocessor Research and Development Center, Peking University, Beijing, China
Dong Tong , Microprocessor Research and Development Center, Peking University, Beijing, China
pp. 387-392

Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis (Abstract)

G. Edward Suh , School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA
Mohamed Ismail , School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA
pp. 393-400

Parameterized free space redistribution for engineering change in placement of integrated circuits (Abstract)

Suhasini Rege , IBM, Bangalore, India
Taraneh Taghavi , IBM, San Diego, CA
Shyam Ramji , IBM, Hopewell Junction, NY
Frank Musante , IBM, Hopewell Junction, NY
pp. 401-406

Providing cost-effective on-chip network bandwidth in GPGPUs (Abstract)

Soojung Ryu , Samsung Advanced Institute of Technology, Suwon, Korea
Woong Seo , Samsung Advanced Institute of Technology, Suwon, Korea
Hanjoon Kim , KAIST, Daejeon, Korea
Yeongon Cho , Samsung Advanced Institute of Technology, Suwon, Korea
John Kim , KAIST, Daejeon, Korea
pp. 407-412

3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores (Abstract)

Ahmed Louri , Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721
Randy Morris , Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701
Avinash Karanth Kodi , Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701
pp. 413-418

Adaptive Backpressure: Efficient buffer management for on-chip networks (Abstract)

George Michelogiannakis , Department of Electrical Engineering, Stanford University, Stanford, CA, USA
William J. Dally , Department of Electrical Engineering, Stanford University, Stanford, CA, USA
Daniel U. Becker , Department of Electrical Engineering, Stanford University, Stanford, CA, USA
Nan Jiang , Department of Electrical Engineering, Stanford University, Stanford, CA, USA
pp. 419-426

A novel profiled side-channel attack in presence of high Algorithmic Noise (Abstract)

Mostafa Taha , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
Patrick Schaumont , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA
pp. 433-438

Architecture and design flow for a debug event distribution interconnect (Abstract)

Kees Goossens , Electronic Systems Group, Faculty of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Arnaldo Azevedo , Department of Software and Computer Technology, Delft University of Technology, Delft, The Netherlands
Bart Vermeulen , NXP Semiconductors, Eindhoven, The Netherlands
pp. 439-444

MSE minimization and fault-tolerant data fusion for multi-sensor systems (Abstract)

Zeljko Zilic , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
Benjamin Nahill , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
Katarzyna Radecka , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
Omid Sarbishei , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
Atena Roshan Fekr , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
Majid Janidarmian , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
pp. 445-452

Locating faults in application-dependent interconnects of SRAM based FPGAs (Abstract)

Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, USA
T. Nandha Kumar , Department of Electrical and Electronic Engineering, The University of Nottingham, Semenyih, Malaysia
Haider A. F. Almurib , Department of Electrical and Electronic Engineering, The University of Nottingham, Semenyih, Malaysia
pp. 453-459

Timing-test scheduling for constraint-graph based post-silicon skew tuning (Abstract)

Mineo Kaneko , School on Information Science, Japan Advanced Institute of Science and Technology, Asahidai, Nomi-shi, Ishikawa 923-1292, Japan
pp. 460-465

Adaptive memory architecture for real-time image warping (Abstract)

Luc Claesen , Expertise Centre for Digital Media, Hasselt University - tUL - IBBT, Diepenbeek, Belgium
Yun Pan , Institute of VLSI Design, Zhejiang University, Hangzhou, China
Andy Motten , Expertise Centre for Digital Media, Hasselt University - tUL - IBBT, Diepenbeek, Belgium
pp. 466-471

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance (Abstract)

Antonio Rubio , Department d'Enginyeria Electronica, Universitat Politecnica de Catalunya, Barcelona, Spain
Antonio Gonzalez , Intel Barcelona Research Center, Intel Labs-UPC, Barcelona, Spain
Dan Alexandrescu , Engineering Division, iRoC Technologies, Grenoble, France
Enrico Costenaro , Engineering Division, iRoC Technologies, Grenoble, France
Ramon Canal , Department d'Arquitectura de Computadors, Universitat Politecnica de Catalunya, Barcelona, Spain
Shrikanth Ganapathy , Department d'Arquitectura de Computadors, Universitat Politecnica de Catalunya, Barcelona, Spain
pp. 472-477

Engineering crossbar based emerging memory technologies (Abstract)

Ozgur Sinanoglu , Department of Engineering, New York University, Abu Dhabi, Abu Dhabi, UAE
Ramesh Karri , Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, Brooklyn, USA
Sachhidh Kannan , Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, Brooklyn, USA
Jeyavijayan Rajendran , Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, Brooklyn, USA
pp. 478-479

Protecting pipelined asynchronous communication channels against single event upsets (Abstract)

Martin Lampacher , Institute of Computer Engineering, Vienna University of Technology, Austria
Jakob Lechner , Institute of Computer Engineering, Vienna University of Technology, Austria
pp. 480-481

Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design (Abstract)

Ayan Mandal , Texas A&M University, College Station, TX 77843
Sunil P. Khatri , Texas A&M University, College Station, TX 77843
Rabi N. Mahapatra , Texas A&M University, College Station, TX 77843
pp. 482-483

A case for small row buffers in non-volatile main memories (Abstract)

Jing Li , IBM T.J. Watson Research Center
Onur Mutlu , Carnegie Mellon University
Justin Meza , Carnegie Mellon University
pp. 484-485

Energy modelling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoC (Abstract)

Eric Senn , Lab-STICC, Université de Bretagne Sud, France
Mickael Lanoe , Lab-STICC, Université de Bretagne Sud, France
pp. 486-487

Efficient code compression for coarse grained reconfigurable architectures (Abstract)

Soojung Ryu , Samsung Advanced Institute of Technology (SAIT), Yongin, Korea
Moo-Kyoung Chung , Samsung Advanced Institute of Technology (SAIT), Yongin, Korea
Yeon-Gon Cho , Samsung Advanced Institute of Technology (SAIT), Yongin, Korea
pp. 488-489

Integration of correct-by-construction BIP models into the MetroII design space exploration flow (Abstract)

Roberto Passerone , University of Trento, Italy
Marius Bozga , VERIMAG, Grenoble, France
Alena Simalatsar , EPFL, Lausanne, Switzerland
Liangpeng Guo , University of California, Berkeley, USA
pp. 490-491

The performance of hypermesh NoCs in FPGAs (Abstract)

M. Binesh Marvasti , Department of ECE, McMaster University, Hamilton, Canada
T. H. Szymanski , Department of ECE, McMaster University, Hamilton, Canada
pp. 492-493

Distributed thermal-aware task scheduling for 3D Network-on-Chip (Abstract)

Hao Yu , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Yingnan Cui , School of Computer Engineering, Nanyang Technological University, Singapore
Wei Zhang , School of Computer Engineering, Nanyang Technological University, Singapore
pp. 494-495

System level modeling of real-time embedded software (Abstract)

Samar Abdi , Concordia University, Montreal, Canada
Doug Regehr , Research In Motion, Waterloo, Canada
Frederic Risacher , Research In Motion, Waterloo, Canada
Richard Lee , Concordia University, Montreal, Canada
pp. 496-497

A 3D stacked high performance scalable architecture for 3D Fourier Transform (Abstract)

Sorin D. Cotofana , Delft University of Technology, The Netherlands
George R. Voicu , Delft University of Technology, The Netherlands
Marius Enachescu , Delft University of Technology, The Netherlands
pp. 498-499

Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors (Abstract)

Sangyeun Cho , Computer Science Department, University of Pittsburgh, Pittsburgh, USA
Yeon-Gon Cho , Samsung Advanced Institute of Technology (SAIT), Yongin, Korea
Soojung Ryu , Samsung Advanced Institute of Technology (SAIT), Yongin, Korea
Moo-Kyoung Chung , Samsung Advanced Institute of Technology (SAIT), Yongin, Korea
Kiyeon Lee , Computer Science Department, University of Pittsburgh, Pittsburgh, USA
pp. 500-501

Dynamic warp resizing: Analysis and benefits in high-performance SIMT (Abstract)

Ahmad Khonsari , School of ECE University of Tehran
Amirali Baniasadi , ECE Department University of Victoria
Ahmad Lashgar , School of ECE University of Tehran
pp. 502-503

Post-layout OPE-predicted redundant wire insertion for clock skew minimization (Abstract)

Jin-Tai Yan , Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C.
Zhi-Wei Chen , College of Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C.
pp. 504-505

Track assignment considering crosstalk-induced performance degradation (Abstract)

Qiong Zhao , Department of ECE, Texas A&M University
Jiang Hu , Department of ECE, Texas A&M University
pp. 506-507

DOC: Fast and accurate congestion analysis for global routing (Abstract)

Sanghamitra Roy , BRIDGE Lab, Electrical and Computer Engineering, Utah State University
Yiding Han , BRIDGE Lab, Electrical and Computer Engineering, Utah State University
Koushik Chakraborty , BRIDGE Lab, Electrical and Computer Engineering, Utah State University
pp. 508-509

Efficient verification of out-of-order behaviors with relaxed scoreboards (Abstract)

Luiz C. V. dos Santos , Federal University of Santa Catarina, Computer Science Department, Florianópolis, SC, Brazil
Gabriel A. G. Andrade , Federal University of Santa Catarina, Computer Science Department, Florianópolis, SC, Brazil
Leandro S. Freitas , Federal University of Santa Catarina, Computer Science Department, Florianópolis, SC, Brazil
pp. 510-511

ECC string: Flexible ECC management for low-cost error protection of L2 caches (Abstract)

Jeongkyu Hong , Dept. of Computer Science, Korea Advanced Institute of Science Technology, Daejeon, Korea
Soontae Kim , Dept. of Computer Science, Korea Advanced Institute of Science Technology, Daejeon, Korea
pp. 512-513

Non-enumerative generation of statistical path delays for ATPG (Abstract)

Sreenivas Gangadhar , Intel Folsom, CA 95630, USA
Rathish Jayabharathi , Intel Folsom, CA 95630, USA
Spyros Tragoudas , ECE Department, Southern Illinois University, Carbondale, IL 62901, USA
Ahish Mysore Somashekar , ECE Department, Southern Illinois University, Carbondale, IL 62901, USA
pp. 514-515

Modeling economics of LSI design and manufacturing for test design selection (Abstract)

Tomoo Inoue , School of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan
Tsuyoshi Iwagaki , School of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan
Noboru Shimizu , School of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan
Hideyuki Ichihara , School of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan
pp. 516-517

Balancing performance and fault detection for GPGPU workloads (Abstract)

Ramesh Karri , Polytechnic Institute of New York University, Brooklyn, NY, 11201
Jerry B. Backer , Polytechnic Institute of New York University, Brooklyn, NY, 11201
pp. 518-519

Ring oscillator physical unclonable function with multi level supply voltages (Abstract)

Shohreh Sharif Mansouri , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm
Elena Dubrova , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm
pp. 520-521

Automatic assertion extraction in gate-level simulation using GPGPUs (Abstract)

Takeshi Matsumoto , VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan
Masahiro Fujita , VLSI Design and Education Center, The University of Tokyo / JST CREST, Tokyo, Japan
Shohei Ono , Dept. of Elect. Eng. and Inf. Syst., The University of Tokyo, Tokyo, Japan
pp. 522-523

[Copyright notice] (Abstract)

pp. i

Table of contents (Abstract)

pp. ii-x

Welcome to ICCD 2012! (Abstract)

pp. xi-xx

Author index (Abstract)

pp. 524-527
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