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2012 IEEE 30th International Conference on Computer Design (ICCD) (2012)
Montreal, QC, Canada Canada
Sept. 30, 2012 to Oct. 3, 2012
ISSN: 1063-6404
ISBN: 978-1-4673-3051-0
pp: 439-444
Kees Goossens , Electronic Systems Group, Faculty of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Arnaldo Azevedo , Department of Software and Computer Technology, Delft University of Technology, Delft, The Netherlands
Bart Vermeulen , NXP Semiconductors, Eindhoven, The Netherlands
ABSTRACT
In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas of the Network-on-Chip based Multi-Processor System-on-Chip. The EDI replicates the NoC topology with an EDI node instantiated for each underlying NoC data module. Contention in the EDI node is handled by replicating the EDI in layers. The EDI generation is automatic, and uses as input the cross-triggering patterns that are not required to follow the communication patterns in the NoC. The generation and routing tool is also presented in this paper. The EDI is evaluated with four different implementations varying complexity and handling of contention. The area of a single EDI Layer is around 0.9% of the area occupied by the tested NoCs, using the lower area implementation. These results show that the proposed implementation of the EDI incurs low cost on the overall system.
INDEX TERMS
Monitoring, Topology, Routing, Registers, Complexity theory, IP networks
CITATION

K. Goossens, A. Azevedo and B. Vermeulen, "Architecture and design flow for a debug event distribution interconnect," 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)(ICCD), Montreal, QC, 2012, pp. 439-444.
doi:10.1109/ICCD.2012.6378676
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