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2012 IEEE 30th International Conference on Computer Design (ICCD) (2012)
Montreal, QC, Canada Canada
Sept. 30, 2012 to Oct. 3, 2012
ISSN: 1063-6404
ISBN: 978-1-4673-3051-0
pp: 94-101
Ken Mai , DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Osman S. Unsal , Barcelona Supercomputing Center, C/Jordi Girona 29, Barcelona, Spain
Erich F. Haratsch , LSI Corporation, 1110 American Parkway NE, Allentown, PA
Adrian Cristal , Barcelona Supercomputing Center, C/Jordi Girona 29, Barcelona, Spain
Yu Cai , DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Gulay Yalcin , Barcelona Supercomputing Center, C/Jordi Girona 29, Barcelona, Spain
Onur Mutlu , DSSC, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
ABSTRACT
With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.
INDEX TERMS
Error correction codes, Flash memory, Bit error rate, Threshold voltage, Nonvolatile memory, Programming, multi-level cell (MLC), NAND Flash, reliability, error correction
CITATION

K. Mai et al., "Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime," 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)(ICCD), Montreal, QC, 2012, pp. 94-101.
doi:10.1109/ICCD.2012.6378623
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