The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (2011)
Amherst, MA, USA
Oct. 9, 2011 to Oct. 12, 2011
ISBN: 978-1-4577-1953-0
TABLE OF CONTENTS
Papers

Title page (PDF)

pp. c1

Memory coherence in the age of multicores (Abstract)

Myong Hyon Cho , Massachusetts Institute of Technology, Cambridge, USA
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge, USA
Keun Sup Shim , Massachusetts Institute of Technology, Cambridge, USA
Mieszko Lis , Massachusetts Institute of Technology, Cambridge, USA
pp. 1-8

The convergence of HPC and embedded systems in our heterogeneous computing future (Abstract)

David Akodes , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
David Kaeli , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
pp. 9-11

A GALS Network-on-Chip based on rationally-related frequencies (Abstract)

Ahmed Hemani , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm, USA
Jean-Michel Chabloz , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm, USA
pp. 12-18

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs (Abstract)

Baris Taskin , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104, USA
Ankit More , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104, USA
pp. 19-24

Leveraging torus topology with deadlock recovery for cost-efficient on-chip network (Abstract)

John Kim , Department of Computer Science, KAIST, Daejeon, Korea
Minjeong Shin , Department of Computer Science, KAIST, Daejeon, Korea
pp. 25-30

A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip (Abstract)

Luca P. Carloni , Columbia University, Dept. of Computer Science, New York, 10027, USA
Andrea Vesco , Istituto Superiore Mario Boella, 10138 Torino, Italy
Nicola Concer , Columbia University, Dept. of Computer Science, New York, 10027, USA
Riccardo Scopigno , Istituto Superiore Mario Boella, 10138 Torino, Italy
pp. 31-38

DPPC: Dynamic power partitioning and capping in chip multiprocessors (Abstract)

Kai Ma , The Ohio State University, USA
Xiaorui Wang , The Ohio State University, USA
Yefu Wang , University of Tennessee, Knoxville, USA
pp. 39-44

A machine learning approach to modeling power and performance of chip multiprocessors (Abstract)

Kushal Datta , Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, USA
Arun Ravindran , Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, USA
Arindam Mukherjee , Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, USA
Changshu Zhang , Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, USA
Bharat Joshi , Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, USA
pp. 45-50

Using content-aware bitcells to reduce static energy dissipation (Abstract)

Fahrettin Koc , TOBB University of Economics and Technology, Ankara, Turkey
Osman Seckin Simsek , TOBB University of Economics and Technology, Ankara, Turkey
Oguz Ergin , TOBB University of Economics and Technology, Ankara, Turkey
pp. 51-56

Tree structured analysis on GPU power study (Abstract)

Lu Peng , Department of ECE, Louisiana State University, Baton Rouge, USA
Bin Li , Department of Experimental Statistics, Louisiana State University, Baton Rouge, USA
Jih-kwon Peir , Department of CISE, University of Florida, Gainesville, USA
Ying Zhang , Department of ECE, Louisiana State University, Baton Rouge, USA
Jianmin Chen , Department of CISE, University of Florida, Gainesville, USA
pp. 57-64

Pre-assignment RDL routing via extraction of maximal net sequence (Abstract)

Zhi-Wei Chen , College of Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C.
Jin-Tai Yan , Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C.
pp. 65-70

Path aware event scheduler in HoldAdvisor for fixing min timing violations (Abstract)

Raghu Pattipati , Microelectronics Group, Oracle America, Inc., Santa Clara, CA, U.S.A.
Harshinder Bagga , Microelectronics Group, Oracle America, Inc., Santa Clara, CA, U.S.A.
Richard Cheung , Microelectronics Group, Oracle America, Inc., Santa Clara, CA, U.S.A.
Tong Xiao , Microelectronics Group, Oracle America, Inc., Santa Clara, CA, U.S.A.
George J. Chen , Microelectronics Group, Oracle America, Inc., Santa Clara, CA, U.S.A.
pp. 71-77

A tool set for the design of asynchronous circuits with bundled-data implementation (Abstract)

Naohiro Hamada , The University of Aizu, Japan
Minoru Iizuka , The University of Aizu, Japan
Hiroshi Saito , The University of Aizu, Japan
Minoru Yoshinaga , Renesas Micro Systems Co., Ltd., Japan
Ryoichi Yamaguchi , Renesas Micro Systems Co., Ltd., Japan
pp. 78-83

Applying verification intention for design customization via property mining under constrained testbenches (Abstract)

Sy-Yen Kuo , GIEE, National Taiwan University, Taipei, Taiwan
Chih-Neng Chung , GIEE, National Taiwan University, Taipei, Taiwan
Kai-Hui Chang , Avery Design System, Inc., Andover, MA, USA
Chia-Wei Chang , EE, National Central University, Jhongli, Taiwan
pp. 84-89

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores (Abstract)

Hsien-Hsin S. Lee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USa
Shreepad Panth , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USa
Xin Zhao , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USa
Dean L. Lewis , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USa
Sung Kyu Lim , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USa
pp. 90-95

Reduced complexity test generation algorithms for transition fault diagnosis (Abstract)

Vishwani D. Agrawal , Auburn University, Department of Electrical and Computer Engineering, AL 36849, USA
Yu Zhang , Auburn University, Department of Electrical and Computer Engineering, AL 36849, USA
pp. 96-101

Enhanced symbolic simulation of a round-robin arbiter (Abstract)

Xiaoyu Song , ECE Department, Portland State University, Oregon, USA
Yongjian Li , State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, Beijing, China
Naiju Zeng , State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, Beijing, China
William N. N. Hung , Synopsys Inc., Mountain View, California, USA
pp. 102-107

Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation (Abstract)

E. Barke , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
D. Zaum , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
S. Hoelldampf , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
M. Olbrich , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
pp. 108-112

An optimized scaled neural branch predictor (Abstract)

Daniel A. Jimenez , Department of Computer Science, The University of Texas at San Antonio, USA
pp. 113-118

TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers (Abstract)

Xu Cheng , Microprocessor Research & Development Center, Peking University, Beijing, China
Zichao Xie , Microprocessor Research & Development Center, Peking University, Beijing, China
Xiaoyin Wang , Microprocessor Research & Development Center, Peking University, Beijing, China
Qinqing Shi , Microprocessor Research & Development Center, Peking University, Beijing, China
Dong Tong , Microprocessor Research & Development Center, Peking University, Beijing, China
Mingkai Huang , Microprocessor Research & Development Center, Peking University, Beijing, China
pp. 119-126

Simultaneous continual flow pipeline architecture (Abstract)

Haitham Akkary , Department of Electrical and Computer Engineering, American University of Beirut, Lebanon
Komal Jothi , Department of Electrical and Computer Engineering, American University of Beirut, Lebanon
Mageda Sharafeddine , Department of Electrical and Computer Engineering, American University of Beirut, Lebanon
pp. 127-134

Thread-aware dynamic shared cache compression in multi-core processors (Abstract)

Gabriel H. Loh , Advanced Micro Devices, Inc., USA
Yuejian Xie , Georgia Institute of Technology, USA
pp. 135-141

Memristor-based IMPLY logic design procedure (Abstract)

Uri C. Weiser , Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 ISRAEL
Avinoam Kolodny , Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 ISRAEL
Eby G. Friedman , Department of Electrical and Computer Engineering, University of Rochester, NY 14627 USA
Shahar Kvatinsky , Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 ISRAEL
pp. 142-147

A memristor-based memory cell using ambipolar operation (Abstract)

Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA
Pilin Junsangsri , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA
pp. 148-153

Using stochastic computing to implement digital image processing algorithms (Abstract)

Peng Li , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, USA, 55812
David J. Lilja , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, USA, 55812
pp. 154-161

A simple pipelined squaring circuit for DSP (Abstract)

Aleksej Avramovic , University of Banja Luka, Faculty of Electrical Engineering, Bosnia and Herzegovina
Vladimir Risojevic , University of Banja Luka, Faculty of Electrical Engineering, Bosnia and Herzegovina
Patricio Bulic , University of Ljubljana, Faculty of Computer and Information Science, Slovenia
Zdenka Babic , University of Banja Luka, Faculty of Electrical Engineering, Bosnia and Herzegovina
pp. 162-167

AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices (Abstract)

Chris Ohlsen , Colorado State University, Department of Electrical and Computer Engineering, Fort Collins, U.S.A.
Sudeep Pasricha , Colorado State University, Department of Electrical and Computer Engineering, Fort Collins, U.S.A.
Brad K. Donohoo , Colorado State University, Department of Electrical and Computer Engineering, Fort Collins, U.S.A.
pp. 168-174

Energy-efficient multi-level cell phase-change memory system with data encoding (Abstract)

Dimin Niu , Department of Computer Science and Engineering, Pennsylvania State University, University Park, USA 16802
Jue Wang , Department of Computer Science and Engineering, Pennsylvania State University, University Park, USA 16802
Guangyu Sun , Department of Computer Science and Engineering, Pennsylvania State University, University Park, USA 16802
Yuan Xie , Department of Computer Science and Engineering, Pennsylvania State University, University Park, USA 16802
Xiangyu Dong , Department of Computer Science and Engineering, Pennsylvania State University, University Park, USA 16802
pp. 175-182

Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware accelerators (Abstract)

Yen-Kuan Wu , Electrical and Computer Engineering Dept., University of California at San Diego, La Jolla, USA
Shervin Sharifi , Computer Science and Engineering Dept., University of California at San Diego, La Jolla, USA
Tajana Simunic Rosing , Computer Science and Engineering Dept., University of California at San Diego, La Jolla, USA
pp. 183-189

Energy-aware Standby-Sparing Technique for periodic real-time applications (Abstract)

Dakai Zhu , Department of Computer Science, University of Texas at San Antonio, 78249, USA
Mohammad A. Haque , Department of Computer Science, George Mason University, Fairfax VA 22030, USA
Hakan Aydin , Department of Computer Science, George Mason University, Fairfax VA 22030, USA
pp. 190-197

A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems (Abstract)

Arslan Munir , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Sanjay Ranka , Department of Computer and Information Science and Engineering, University of Florida, Gainesville, USA
Ann Gordon-Ross , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
pp. 198-205

A study on relating redundancy removal in classical circuits to reversible mapping (Abstract)

Yu Pang , College of Electronic Engineering, Chongqing University of Posts and Telecommunications, China
Katarzyna Radecka , Department of Electrical and Electronic Engineering, McGill University, Montreal, Canada
Sayeeda Sultana , Department of Electrical and Electronic Engineering, McGill University, Montreal, Canada
pp. 206-211

Positive Davio-based synthesis algorithm for reversible logic (Abstract)

Jinzhao Lin , College of Electronic Engineering, Chongqing University of Posts and Telecommunications, China
Yu Pang , College of Electronic Engineering, Chongqing University of Posts and Telecommunications, China
Sayeeda Sultana , Dept. of Electrical & Computer Engineering, McGill University, Montreal, Canada
Shaoquan Wang , College of Electronic Engineering, Chongqing University of Posts and Telecommunications, China
Zhilong He , College of Electronic Engineering, Chongqing University of Posts and Telecommunications, China
Katarzyna Radecka , Dept. of Electrical & Computer Engineering, McGill University, Montreal, Canada
pp. 212-218

Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA (Abstract)

Yong Dou , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, Changsha, China 410073
Yuanwu Lei , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, Changsha, China 410073
Jie Zhou , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, Changsha, China 410073
Li Shen , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, Changsha, China 410073
Song Guo , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, Changsha, China 410073
pp. 219-225

Fast and compact binary-to-BCD conversion circuits for decimal multiplication (Abstract)

Mohammad Al-Khaleel , Yarmouk University, Irbid, Jordan
Osama Al-Khaleel , Jordan University of Science and Technology, Irbid, Jordan
Zakaria Al-Qudah , Yarmouk University, Irbid, Jordan
Christos A. Papachristou , Case Western Reserve University, Cleveland, OH, USA
Francis G. Wolff , Case Western Reserve University, Cleveland, OH, USA
pp. 226-231

RoShaQ: High-performance on-chip router with shared queues (Abstract)

Anh T. Tran , University of California, Davis, USA
Bevan M. Baas , University of California, Davis, USA
pp. 232-238

Hybrid system level power consumption estimation for FPGA-based MPSoC (Abstract)

Eric Senn , LAB-STICC Université de Bretagne Sud, Lorient, France
Rabie Ben Atitallah , LAMIH, Université de Valenciennes et du Hainaut Cambrésis, France
Santhosh Kumar Rethinagiri , INRIA Lille Nord Europe, Université de Lille1, France
Smail Niar , LAMIH, Université de Valenciennes et du Hainaut Cambrésis, France
Jean-Luc Dekeyser , INRIA Lille Nord Europe, Université de Lille1, France
pp. 239-246

Video quality-driven buffer dimensioning in MPSoC platforms via prioritized frame drops (Abstract)

Samarjit Chakraborty , TU Munich, Germany
Roger Zimmermann , National University of Singapore, Singapore
Deepak Gangadharan , National University of Singapore, Singapore
Haiyang Ma , National University of Singapore, Singapore
pp. 247-252

Techniques for LI-BDN synthesis for hybrid microarchitectural simulation (Abstract)

Zhuo Ruan , Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA
David A. Penry , Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA
Tyler S. Harris , Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA
pp. 253-260

Runtime adaptable concurrent error detection for linear digital systems (Abstract)

Kaijie Wu , University of Illinois at Chicago, ECE, USA
Yu Liu , University of Illinois at Chicago, ECE, USA
pp. 261-266

A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer (Abstract)

Hongguang Ren , School of Computer, National University of Defense Technology, Changsha, China
Wei Shi , School of Computer, National University of Defense Technology, Changsha, China
Cong Liu , School of Computer, National University of Defense Technology, Changsha, China
Li Shen , School of Computer, National University of Defense Technology, Changsha, China
Weixia Xu , School of Computer, National University of Defense Technology, Changsha, China
Zhiying Wang , School of Computer, National University of Defense Technology, Changsha, China
Qiang Dou , School of Computer, National University of Defense Technology, Changsha, China
pp. 267-272

ROA-brick topology for rotary resonant clocks (Abstract)

Ying Teng , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104, USA
Baris Taskin , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104, USA
Jianchao Lu , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104, USA
pp. 273-278

Impact and optimization of lithography-aware regular layout in digital circuit design (Abstract)

Renato P. Ribas , Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Felipe S. Marranghello , Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Vinicius Dal Bem , Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Paulo Butzen , Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Andre I. Reis , Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil
pp. 279-284

Blue team red team approach to hardware trust assessment (Abstract)

Jeyavijayan Rajendran , ECE Department, Polytechnic Institute of NYU, Brooklyn, USA
Vinayaka Jyothi , ECE Department, Polytechnic Institute of NYU, Brooklyn, USA
Ramesh Karri , ECE Department, Polytechnic Institute of NYU, Brooklyn, USA
pp. 285-288

Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection (Abstract)

Phillip Jones , Electrical and Computer Engineering, Iowa State University, Ames, USA
Xinying Wang , Electrical and Computer Engineering, Iowa State University, Ames, USA
Joseph Zambreno , Electrical and Computer Engineering, Iowa State University, Ames, USA
Justin Rilling , Electrical and Computer Engineering, Iowa State University, Ames, USA
David Graziano , Electrical and Computer Engineering, Iowa State University, Ames, USA
Jamin Hitchcock , Electrical and Computer Engineering, Iowa State University, Ames, USA
Tim Meyer , Electrical and Computer Engineering, Iowa State University, Ames, USA
pp. 289-292

Hardware Trojans: The defense and attack of integrated circuits (Abstract)

William H. Robinson , Vanderbilt University EECS Department, Nashville TN, USA
Trey Reece , Vanderbilt University EECS Department, Nashville TN, USA
pp. 293-296

Sequential hardware Trojan: Side-channel aware design and placement (Abstract)

Tatini Mal-Sarkar , Hathaway Brown High School, Cleveland, OH, USA
Seetharam Narasimhan , Electrical Engineering and Computer Science Department, Case Western Reserve University, USA
Xinmu Wang , Electrical Engineering and Computer Science Department, Case Western Reserve University, USA
Swarup Bhunia , Electrical Engineering and Computer Science Department, Case Western Reserve University, USA
Aswin Krishna , Electrical Engineering and Computer Science Department, Case Western Reserve University, USA
pp. 297-300

Implementing hardware Trojans: Experiences from a hardware Trojan challenge (Abstract)

Ashwin Lakshminarasimhan , University of Massachusetts at Amherst, USA
Sudheendra Srivathsa , University of Massachusetts at Amherst, USA
Vikram B. Suresh , University of Massachusetts at Amherst, USA
Wayne Burelson , University of Massachusetts at Amherst, USA
Georg T. Becker , University of Massachusetts at Amherst, USA
Lang Lin , University of Massachusetts at Amherst, USA
pp. 301-304

Is single-scheme Trojan prevention sufficient? (Abstract)

Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, USA
Yier Jin , Department of Electrical Engineering, Yale University, USA
pp. 305-308

Red team: Design of intelligent hardware trojans with known defense schemes (Abstract)

Nicholas Tuzzio , ECE Department, University of Connecticut, USA
Xuehui Zhang , ECE Department, University of Connecticut, USA
Mohammad Tehranipoor , ECE Department, University of Connecticut, USA
pp. 309-312

Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path (Abstract)

Kyohei Yamaguchi , Department of Electrical Engineering and Computer Science, Nagoya University, Japan
Yuya Kora , Department of Computational Science and Engineering, Nagoya University, Japan
Hideki Ando , Department of Electrical Engineering and Computer Science, Nagoya University, Japan
pp. 313-319

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset (Abstract)

Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA
Sheng Lin , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA
Yong-Bin Kim , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA
pp. 320-325

Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology (Abstract)

Georgios Karakonstantis , Swiss Federal Institute of Technology (EPFL), Switzerland
Kaushik Roy , Nanoelectronic Research Lab, Purdue University, USA
Hamid Mahmoodi , NeCRL Group, San Francisco State University, USA
Georgios Panagopoulos , Nanoelectronic Research Lab, Purdue University, USA
Dag Wisland , Nanoelectronics Group, University of Oslo, Norway
Jens Kargaard Madsen , Aarhus School of Engineering, Aarhus University, Denmark
Farshad Moradi , Nanoelectronics Group, University of Oslo, Norway
pp. 326-331

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors (Abstract)

Shrikanth Ganapathy , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Antonio Gonzalez , Intel Barcelona Research Center, Intel Labs-UPC, Barcelona, Spain
Antonio Rubio , Department d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Barcelona, Spain
Ramon Canal , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
pp. 332-338

Adaptable architectures for distributed visual target tracking (Abstract)

Ankur Srivastava , Department of Electrical and Computer Engineering, University of Maryland, College Park, USA
Domenic Forte , Department of Electrical and Computer Engineering, University of Maryland, College Park, USA
pp. 339-345

Improving GPU Robustness by making use of faulty parts (Abstract)

Ramesh Karri , ECE Department, Polytechnic Institute of NYU, New York, USA
Artem Durytskyy , ECE Department, Polytechnic Institute of NYU, New York, USA
Mohamed Zahran , ECE Department, Polytechnic Institute of NYU, New York, USA
pp. 346-351

Functional correctness for CMP interconnects (Abstract)

Ritesh Parikh , Department of Computer Science and Engineering, University of Michigan, USA
Rawan Abdel-Khalek , Department of Computer Science and Engineering, University of Michigan, USA
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan, USA
Andrew DeOrio , Department of Computer Science and Engineering, University of Michigan, USA
pp. 352-359

Task model for on-chip communication infrastructure design for multicore systems (Abstract)

Kunal Ganeshpure , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
Bharath Phanibhushana , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
pp. 360-365

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory (Abstract)

Guangyu Sun , Center for Energy-Efficient, Computing and Applications, Peking University, China
Jude A. Rivers , IBM Thomas J. Watson Research Center, USA
Yuan Xie , Computer Science and Engineering Department, Pennsylvania State University, USA
Eren Kursun , IBM Thomas J. Watson Research Center, USA
pp. 366-372

A morphable phase change memory architecture considering frequent zero values (Abstract)

Hamid Sarbazi-Azad , HPCAN Lab, Computer Engineering Department, Sharif University of Technology, Tehran, Iran
Amin Jadidi , HPCAN Lab, Computer Engineering Department, Sharif University of Technology, Tehran, Iran
Ali Shafiee , HPCAN Lab, Computer Engineering Department, Sharif University of Technology, Tehran, Iran
Mohammad Arjomand , HPCAN Lab, Computer Engineering Department, Sharif University of Technology, Tehran, Iran
pp. 373-380

An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems (Abstract)

Seungcheol Baek , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Hyung Gyu Lee , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Jongman Kim , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Chrysostomos Nicopoulos , Department of Electrical and Computer Engineering, University of Cyprus, Cyprus
pp. 381-387

The DIMM tree architecture: A high bandwidth and scalable memory system (Abstract)

Jason Cong , Computer Science Department, University of California, Los Angeles, USA
Kanit Therdsteerasukdi , Computer Science Department, University of California, Los Angeles, USA
Glenn Reinman , Computer Science Department, University of California, Los Angeles, USA
Gyung-Su Byun , Computer Science and Electrical Engineering Department, West Virginia University, Morgantown, USA
Jeremy Ir , Electrical Engineering Department, University of California, Los Angeles, USA
M.F. Chang , Electrical Engineering Department, University of California, Los Angeles, USA
pp. 388-395

CPACT - The conditional parameter adjustment cache tuner for dual-core architectures (Abstract)

Ann Gordon-Ross , Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA
Marisha Rawlins , Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA
pp. 396-403

SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time (Abstract)

Valentina Salapura , IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Michael Gschwind , IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Sally A. McKee , Charlmers University of Technology, Göteborg, Sweden
Catherine Trammell , IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
pp. 404-410

ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores (Abstract)

Farrukh Hijaz , University of Massachusetts, Lowell, USA
Mieszko Lis , Massachusetts Institute of Technology, Cambridge, USA
Anant Agarwal , Massachusetts Institute of Technology, Cambridge, USA
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge, USA
Omer Khan , University of Massachusetts, Lowell, USA
Henry Hoffmann , Massachusetts Institute of Technology, Cambridge, USA
pp. 411-418

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors (Abstract)

Kewal K. Saluja , University of Wisconsin-Madison, USA
Virendra Singh , Indian Institute of Science, Bangalore, India
Pramod Subramanyan , Princeton University, NJ, USA
Erik Larsson , Linköping University, Sweden
pp. 419-426

Analysis of on-chip interconnection network interface reliability in multicore systems (Abstract)

Sudeep Pasricha , Colorado State University, Fort Collins, U.S.A
Yi Xiang , Colorado State University, Fort Collins, U.S.A
Yong Zou , Colorado State University, Fort Collins, U.S.A
pp. 427-428

AIG rewriting using 5-input cuts (Abstract)

Elena Dubrova , Royal Institute of Technology, ES/ICT/KTH, 164 46 Kista, Sweden
Nan Li , Royal Institute of Technology, ES/ICT/KTH, 164 46 Kista, Sweden
pp. 429-430

FIMSIM: A fault injection infrastructure for microarchitectural simulators (Abstract)

Adrian Cristal , Barcelona Supercomputing Center, Spain
Mateo Valero , Barcelona Supercomputing Center, Spain
Gulay Yalcin , Barcelona Supercomputing Center, Spain
Osman S. Unsal , Barcelona Supercomputing Center, Spain
pp. 431-432

A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults (Abstract)

Reyhaneh Jabbarvand Behrouz , Department of Computer Engineering, Sharif University of Technology, Tehran, Islamic Republic of Iran
Mehdi Modarressi , Department of Electrical and Computer Engineering, University of Tehran, Tehran, Islamic Republic of Iran
Hamid Sarbazi Azad , Department of Computer Engineering, Sharif University of Technology, Tehran, Islamic Republic of Iran
pp. 433-434

3D vs. 2D analysis of FinFET logic gates under process variations (Abstract)

Niraj K. Jha , Department of Electrical Engineering, Princeton University, NJ, 08544, USA
Sourindra Chaudhuri , Department of Electrical Engineering, Princeton University, NJ, 08544, USA
pp. 435-436

Precise exception support for decoupled run-time monitoring architectures (Abstract)

G. Edward Suh , Cornell University, Ithaca, NY 14853, USA
Daniel Y. Deng , Cornell University, Ithaca, NY 14853, USA
pp. 437-438

Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology (Abstract)

Hamid Mahmoodi , San Francisco State University, USA
Vikram G Rao , San Francisco State University, USA
pp. 439-440

Towards a tool for implementing delay-free ECC in embedded memories (Abstract)

Michael Nicolaidis , TIMA Laboratory (CNRS, Grenoble INP, UJF), France
Nacer-Eddine Zergainoh , TIMA Laboratory (CNRS, Grenoble INP, UJF), France
Thierry Bonnoit , TIMA Laboratory (CNRS, Grenoble INP, UJF), France
pp. 441-442

A novel software-based defect-tolerance approach for application-specific embedded systems (Abstract)

Sandeep Gupta , Electrical Engineering Department, CA, US
Da Cheng , Electrical Engineering Department, CA, US
pp. 443-444

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling (Abstract)

Fahimeh Jafari , Royal Institute of Technology (KTH), Sweden
Zhonghai Lu , Royal Institute of Technology (KTH), Sweden
Axel Jantsch , Royal Institute of Technology (KTH), Sweden
pp. 445-446

Comparative analysis of copper and CNT interconnects for H-tree clock distribution (Abstract)

Hamid Mahmoodi , San Francisco State University, USA
Vish Ganti , San Francisco State University, USA
pp. 447-448

Energy aware task mapping algorithm for heterogeneous MPSoC based architectures (Abstract)

Rahul Amin , School of Computing, Clemson University, SC USA
Amr M. A. Hussien , School of Electrical Engineering and Computer Science, University of California, Irvine, USA
Ahmed M. Eltawil , School of Electrical Engineering and Computer Science, University of California, Irvine, USA
Jim Martin , School of Computing, Clemson University, SC USA
pp. 449-450

A novel cryptographic key exchange scheme using resistors (Abstract)

Bradley Johnson , Department of ECE, Texas A&M University, College Station 77843, USA
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station 77843, USA
Alex Ivanov , Department of ECE, Texas A&M University, College Station 77843, USA
Pey-Chang Kent Lin , Department of ECE, Texas A&M University, College Station 77843, USA
pp. 451-452

Low power, high throughput network-on-chip fabric for 3D multicore processors (Abstract)

Vivek S Nandakumar , Dept. of ECE, University of California, Santa Barbara, USA
Malgorzata Marek-Sadowska , Dept. of ECE, University of California, Santa Barbara, USA
pp. 453-454

Static window addition: A new paradigm for the design of variable latency adders (Abstract)

Kai Du , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Kartik Mohanram , Department of Electrical and Computer Engineering, University of Pittsburgh, USA
Peter Varman , Department of Electrical and Computer Engineering, Rice University, Houston, USA
pp. 455-456

Energy-aware and quality-scalable data placement and retrieval for disks in video server environments (Abstract)

Domenic Forte , Department of Electrical and Computer Engineering, University of Maryland, College Park, USA
Ankur Srivastava , Department of Electrical and Computer Engineering, University of Maryland, College Park, USA
pp. 457-458

Author index (PDF)

pp. 459-461
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