The Community for Technology Leaders
2010 IEEE International Conference on Computer Design (2010)
Amsterdam Netherlands
Oct. 3, 2010 to Oct. 6, 2010
ISSN: 1063-6404
ISBN: 978-1-4244-8936-7
TABLE OF CONTENTS

Welcome to ICCD 2010! (PDF)

Georgi Gaydadjiev , TU Delft, The Netherlands
Sofiene Tahar , Concordia University, USA
Lars Svensson , Chalmers University, Sweden
pp. X

Out-of-order retirement of instructions in sequentially consistent multiprocessors (PDF)

R. Ubal , Dept. of Computer Engineering (DISCA), Universidad Politécnica de Valencia, Spain
J. Sahuquillo , Dept. of Computer Engineering (DISCA), Universidad Politécnica de Valencia, Spain
S. Petit , Dept. of Computer Engineering (DISCA), Universidad Politécnica de Valencia, Spain
P. Lopez , Dept. of Computer Engineering (DISCA), Universidad Politécnica de Valencia, Spain
D. Kaeli , Electrical and Computer Engineering Dept., Northeastern University, Boston (MA), USA
pp. 1-8

Efficient MIMD architectures for high-performance ray tracing (PDF)

D. Kopta , University of Utah, School of Computing, USA
J. Spjut , University of Utah, School of Computing, USA
E. Brunvand , University of Utah, School of Computing, USA
A. Davis , University of Utah, School of Computing, USA
pp. 9-16

A study on performance benefits of core morphing in an asymmetric multicore processor (PDF)

Anup Das , Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, USA
Rance Rodrigues , Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, USA
Israel Koren , Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, USA
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, USA
pp. 17-22

Lowering the latency of interfaces for rationally-related frequencies (PDF)

Jean-Michel Chabloz , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm, Sweden
Ahmed Hemani , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm, Sweden
pp. 23-30

High throughput, low set-up time, reconfigurable linear Feedback Shift Registers (PDF)

R.J.M. Nas , ST-Ericsson, Eindhoven, The Netherlands
C.H. van Berkel , ST-Ericsson, The Netherlands
pp. 31-37

Robust and energy-efficient DSP systems via output probability processing (PDF)

Rami A. Abdallah , Coordinated Science Laboratory/ECE Department, University of Illinois at Urbana-Champaign, USA
Naresh R. Shanbhag , Coordinated Science Laboratory/ECE Department, University of Illinois at Urbana-Champaign, USA
pp. 38-44

Optimization of back pressure and throughput for latency insensitive systems (PDF)

Bin Xue , FERMAT Lab, Virginia Tech, Blacksburg, USA
Sandeep K. Shukla , FERMAT Lab, Virginia Tech, Blacksburg, USA
pp. 45-51

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin (PDF)

Yue Qian , School of Computer Science, National University of Defense Technology, China
Zhonghai Lu , School of Information and Communication Technology, Royal Institute of Technology (KTH), Sweden
Qiang Dou , School of Computer Science, National University of Defense Technology, China
pp. 52-59

A flexible simulation methodology and tool for nanoarray-based architectures (PDF)

Stefano Frache , Electronics Department, Politecnico di Torino, Italy
Mariagrazia Graziano , Electronics Department, Politecnico di Torino, Italy
Maurizio Zamboni , Electronics Department, Politecnico di Torino, Italy
pp. 60-67

Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulators (PDF)

Zhuo Ruan , Department of Electrical and Computer Engineering, Brigham Young University, Provo, Utah 84602, U.S.A
Kurtis Cahill , Department of Electrical and Computer Engineering, Brigham Young University, Provo, Utah 84602, U.S.A
David Penry , Department of Electrical and Computer Engineering, Brigham Young University, Provo, Utah 84602, U.S.A
pp. 68-75

Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms (PDF)

Rami Sheikh , North Carolina State University, USA
Mazen Kharbutli , Jordan Univ. of Science and Technology, Jordan
pp. 76-83

Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors (PDF)

Ali Shafiee , CE Department, Sharif University of Technology, Tehran, Iran
Narges Shahidi , CE Department, Sharif University of Technology, Tehran, Iran
Amirali Baniasadi , CE Department, Sharif University of Technology, Tehran, Iran
pp. 84-91

A tag-based cache replacement (PDF)

Chuanjun Zhang , Computer Science Electrical Engineering Department, University of Missouri-Kansas City, USA
Bing Xue , Computer Science Electrical Engineering Department, University of Missouri-Kansas City, USA
pp. 92-97

A voting-based working set assessment scheme for dynamic cache resizing mechanisms (PDF)

Masayuki Sato , Graduate School of Information Sciences, Tohoku University, Japan
Ryusuke Egawa , Cybersicence Center, Tohoku University, Sendai, 980-8578, Japan
Hiroyuki Takizawa , Graduate School of Information Sciences, Tohoku University, Japan
Hiroaki Kobayashi , Cybersicence Center, Tohoku University, Sendai, 980-8578, Japan
pp. 98-105

Insertion policy selection using Decision Tree Analysis (PDF)

Samira Khan , Department of Computer Science, University of Texas at San Antonio, USA
Daniel A. Jimenez , Department of Computer Science, University of Texas at San Antonio, USA
pp. 106-111

Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC (PDF)

Shi-Ting Zhou , The University of Wisconsin-Madison, 53706, U.S.A.
Sumeet Katariya , The University of Wisconsin-Madison, 53706, U.S.A.
Hamid Ghasemi , The University of Wisconsin-Madison, 53706, U.S.A.
Stark Draper , The University of Wisconsin-Madison, 53706, U.S.A.
Nam Sung Kim , The University of Wisconsin-Madison, 53706, U.S.A.
pp. 112-117

Thermal-aware scratchpad memory design and allocation (PDF)

Morteza Damavandpeyma , Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
Sander Stuijk , Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
Twan Basten , Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
Marc Geilen , Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
Henk Corporaal , Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
pp. 118-124

Spintronic logic gates for spintronic data using magnetic tunnel junctions (PDF)

Shruti Patil , Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, USA
Andrew Lyle , Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, USA
Jonathan Harms , Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, USA
David J. Lilja , Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, USA
Jian-Ping Wang , Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, USA
pp. 125-131

On mismatch number distribution of nanocrossbar logic mapping (PDF)

Yehua Su , ECE Department, University of Illinois at Chicago, 60607, USA
Wenjing Rao , ECE Department, University of Illinois at Chicago, 60607, USA
pp. 132-137

Sub-threshold charge recovery circuits (PDF)

Mehrdad Khatir , Department of Computer Engineering, Sharif University of Technology, Azadi St., Tehran, Iran
Hassan Ghasemzadeh Mohammadi , Department of Computer Engineering, Sharif University of Technology, Azadi St., Tehran, Iran
Alireza Ejlali , Department of Computer Engineering, Sharif University of Technology, Azadi St., Tehran, Iran
pp. 138-144

Data rate maximization by adaptive thresholding RF power management under renewable energy (PDF)

Weiguo Tang , Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA
Lei Wang , Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA
pp. 145-150

Practical completion detection for 2-of-N delay-insensitive codes (PDF)

Marco Cannizzaro , Politecnico di Torino, Italy
Weiwei Jiang , Columbia University, USA
Steven M. Nowick , Columbia University, USA
pp. 151-158

Rate-monotonic scheduling for reducing system-wide energy consumption for hard real-time systems (PDF)

Linwei Niu , Department of Math and Computer Science, Claflin University, Orangeburg, SC 29115, USA
pp. 159-165

Design and implementation of a special purpose embedded system for neural machine interface (PDF)

Xiaorong Zhang , Department of Electrical, Computer, and Biomedical Engineering, University of Rhode Island, Kingston, 02881, USA
He Huang , Department of Electrical, Computer, and Biomedical Engineering, University of Rhode Island, Kingston, 02881, USA
Qing Yang , Department of Electrical, Computer, and Biomedical Engineering, University of Rhode Island, Kingston, 02881, USA
pp. 166-172

A control-theoretic energy management for fault-tolerant hard real-time systems (PDF)

Ali Sharif Ahmadian , Sharif University of Technology, Tehran, Iran
Mahdieh Hosseingholi , Sharif University of Technology, Tehran, Iran
Alireza Ejlali , Sharif University of Technology, Tehran, Iran
pp. 173-178

RTOS-aware modeling of embedded hardware/software systems (PDF)

Matthias Muller , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Germany
Joachim Gerlach , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Germany
Wolfgang Rosenstiel , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Germany
pp. 179-186

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems (PDF)

Paolo Burgio , DEIS - University of Bologna - Italy
Martino Ruggiero , DEIS - University of Bologna - Italy
Francesco Esposito , ReTiS - Scuola Sup. S. Anna Pisa - Italy
Mauro Marinoni , ReTiS - Scuola Sup. S. Anna Pisa - Italy
Giorgio Buttazzo , ReTiS - Scuola Sup. S. Anna Pisa - Italy
Luca Benini , DEIS - University of Bologna - Italy
pp. 187-194

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms (PDF)

Glauco Santos , Programa de Pós Graduação em Microeletrônica - Instituto de Informática - UFRGS, Brazil
Tiago Reimann , Programa de Pós Graduação em Microeletrônica - Instituto de Informática - UFRGS, Brazil
Marcelo Johann , Programa de Pós Graduação em Microeletrônica - Instituto de Informática - UFRGS, Brazil
Ricardo Reis , Programa de Pós Graduação em Microeletrônica - Instituto de Informática - UFRGS, Brazil
pp. 195-202

Routability-driven flip-flop merging process for clock power reduction (PDF)

Zhi-Wei Chen , College of Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C
Jin-Tai Yan , Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C
pp. 203-208

Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array (PDF)

Vinayak Honkote , Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA 19104
Baris Taskin , Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA 19104
pp. 209-214

Incremental gate sizing for late process changes (PDF)

John Lee , Electrical Engineering Department, UCLA, USA
Puneet Gupta , Electrical Engineering Department, UCLA, USA
pp. 215-221

Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization (PDF)

Sanghamitra Roy , Electrical and Computer Engineering, Utah State University, USA
Koushik Chakraborty , Electrical and Computer Engineering, Utah State University, USA
pp. 222-228

Boolean factoring with multi-objective goals (PDF)

Mayler G. A. Martins , PGMICRO - Instituto de Informática - UFRGS, Brazil
Leomar Rosa , PGMICRO - Instituto de Informática - UFRGS, Brazil
Anders B. Rasmussen , Nangate Inc., USA
Renato P. Ribas , PGMICRO - Instituto de Informática - UFRGS, Brazil
Andre I. Reis , PGMICRO - Instituto de Informática - UFRGS, Brazil
pp. 229-234

A simple pipelined logarithmic multiplier (PDF)

Patricio Bulic , University of Ljubljana, Faculty of Computer and Information Science, Slovenia
Zdenka Babic , University of Banja Luka, Faculty of Electrical Engineering, Bosnia and Herzegovina
Aleksej Avramovic , University of Banja Luka, Faculty of Electrical Engineering, Bosnia and Herzegovina
pp. 235-240

A radix-10 digit recurrence division unit with a constant digit selection function (PDF)

Malte Baesler , Institute for Reliable Computing, Hamburg University of Technology, Schwarzenbergstr. 95, D-21073, Germany
Sven-Ole Voigt , Institute for Reliable Computing, Hamburg University of Technology, Schwarzenbergstr. 95, D-21073, Germany
Thomas Teufel , Institute for Reliable Computing, Hamburg University of Technology, Schwarzenbergstr. 95, D-21073, Germany
pp. 241-246

A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation (PDF)

Somayeh Timarchi , Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
Mahmood Fazlali , Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
Sorin D. Cotofana , Department of Computer Engineering, TUDelft, Netherlands
pp. 247-252

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms (PDF)

Shohreh Sharif Mansouri , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm, Sweden
Elena Dubrova , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm, Sweden
pp. 253-259

VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture (PDF)

Vaibhav Gupta , School of Electrical and Computer Engineering, Purdue University, USA
Georgios Karakonstantis , School of Electrical and Computer Engineering, Purdue University, USA
Debabrata Mohapatra , School of Electrical and Computer Engineering, Purdue University, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, USA
pp. 260-265

Combined optimal and heuristic approaches for multiple constant multiplication (PDF)

Jason Thong , Department of Electrical and Computer Engineering, McMaster University, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Canada
pp. 266-273

Threads vs. caches: Modeling the behavior of parallel workloads (PDF)

Zvika Guz , EE department, Technion, Israel
Oved Itzhak , EE department, Technion, Israel
Idit Keidar , EE department, Technion, Israel
Avinoam Kolodny , EE department, Technion, Israel
Avi Mendelson , Microsoft Corporation, USA
Uri C. Weiser , EE department, Technion, Israel
pp. 274-281

Predicting the throughput of multiprocessor applications under dynamic workload (PDF)

Peter Poplavko , Eindhoven University of Technology, The Netherlands
Marc Geilen , Eindhoven University of Technology, The Netherlands
Twan Basten , Eindhoven University of Technology, The Netherlands
pp. 282-288

M5 based EDGE architecture modeling (PDF)

Pengfei Gou , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
Qingbo Li , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
Yinghan Jin , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
Qi Zheng , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
Bing Yang , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
Mingyan Yu , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
Jinxiang Wang , Microelectronic Center, Harbin Institute of Technology, Heilongjiang province, China
pp. 289-296

A lightweight run-time scheduler for multitasking multicore stream applications (PDF)

Michael A. Baker , Arizona State University, USA
Karam S. Chatha , Arizona State University, USA
pp. 297-304

Scenario-based design space exploration of MPSoCs (PDF)

Peter van Stralen , Computer System Architecture Group, Informatics Institute, University of Amsterdam, Netherlands
Andy Pimentel , Computer System Architecture Group, Informatics Institute, University of Amsterdam, Netherlands
pp. 305-312

Toward reliable SRAM-based device identification (PDF)

Joonsoo Kim , The University of Texas at Austin, USA
Joonsoo Lee , The University of Texas at Austin, USA
Jacob A. Abraham , The University of Texas at Austin, USA
pp. 313-320

DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time (PDF)

Wei Shi , School of Computer, National University of Defense Technology, China
Zhiying Wang , School of Computer, National University of Defense Technology, China
Hongguang Ren , School of Computer, National University of Defense Technology, China
Ting Cao , Department of computer science, Australian National University, Australia
Wei Chen , School of Computer, National University of Defense Technology, China
Bo Su , School of Computer, National University of Defense Technology, China
Hongyi Lu , School of Computer, National University of Defense Technology, China
pp. 321-327

Using variable clocking to reduce leakage in synchronous circuits (PDF)

Navid Toosizadeh , Department of Electrical and Computer Engineering, University of Toronto, Canada
Safwat G. Zaky , Department of Electrical and Computer Engineering, University of Toronto, Canada
Jianwen Zhu , Department of Electrical and Computer Engineering, University of Toronto, Canada
pp. 328-335

Efficient provably good OPC modeling and its applications to interconnect optimization (PDF)

Shih-Lun Huang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Chung-Wei Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
pp. 336-341

Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU (PDF)

Seokin Hong , Department of Computer Science, Korea Advanced Institute of Science and Technology, Korea
Soontae Kim , Department of Computer Science, Korea Advanced Institute of Science and Technology, Korea
pp. 342-349

Feasibility study of dynamic Trusted Platform Module (PDF)

Arun K. Kanuparthi , Polytechnic Institute of NYU, USA
Mohamed Zahran , Polytechnic Institute of NYU, USA
Ramesh Karri , Polytechnic Institute of NYU, USA
pp. 350-355

Optimal power/performance pipelining for error resilient processors (PDF)

Nicolas Zea , Electrical & Computer Eng. Dept., Univ. of Illinois, Urbana-Champaign, USA
John Sartori , Electrical & Computer Eng. Dept., Univ. of Illinois, Urbana-Champaign, USA
Ben Ahrens , Electrical & Computer Eng. Dept., Univ. of Illinois, Urbana-Champaign, USA
Rakesh Kumar , Electrical & Computer Eng. Dept., Univ. of Illinois, Urbana-Champaign, USA
pp. 356-363

Implicit hints: Embedding hint bits in programs without ISA changes (PDF)

Hans Vandierendonck , Department of Electronics and Information Systems, Ghent University, Belgium
Koen De Bosschere , Department of Electronics and Information Systems, Ghent University, Belgium
pp. 364-369

Countering code injection attacks with TLB and I/O monitoring (PDF)

Dongkyun Ahn , Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA
Gyungho Lee , College of Information and Communications, Korea University, Korea
pp. 370-375

Energy optimal on-line Self-Test of microprocessors in WSN nodes (PDF)

A. Merentitis , Dept. of Informatics & Tel. Univ. of Athens, Greece
A. Paschalis , Dept. of Informatics & Tel. Univ. of Athens, Greece
D. Gizopoulos , Dept. of Informatics, Univ. of Piraeus, Greece
N. Kranitis , Dept. of Informatics & Tel. Univ. of Athens, Greece
pp. 376-383

Temperature-to-power mapping (PDF)

Zhenyu Qi , Dept. of ECE, University of Virginia, Charlottesville, 22904, USA
Brett H. Meyer , Dept. of CS, University of Virginia, Charlottesville, 22904, USA
Wei Huang , IBM Austin Research Lab, TX 78758, USA
Robert J. Ribando , Dept. of Mechanical and Aerospace Engineering, University of Virginia, Charlottesville, 22904, USA
Kevin Skadron , Dept. of CS, University of Virginia, Charlottesville, 22904, USA
Mircea R. Stan , Dept. of ECE, University of Virginia, Charlottesville, 22904, USA
pp. 384-389

Delay test quality maximization through process-aware selection of test set size (PDF)

Baris Arslan , Computer Science and Engineering, University of California, San Diego, La Jolla, 92093, USA
Alex Orailoglu , Computer Science and Engineering, University of California, San Diego, La Jolla, 92093, USA
pp. 390-395

Crosstalk modeling to predict channel delay in Network-on-Chips (PDF)

A. Patooghy , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
S.G. Miremadi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
M. Shafaei , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 396-401

Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging (PDF)

Yeonbok Lee , Department of Electronics Engineering and Information Systems, The University of Tokyo, Japan
Takeshi Matsumoto , VLSI Design and Education Center, University of Tokyo, Japan
Masahiro Fujita , VLSI Design and Education Center, University of Tokyo, Japan
pp. 402-408

An energy model for graphics processing units (PDF)

Jeff Pool , Dept. of Computer Science, University of North Carolina-Chapel Hill, USA
Anselmo Lastra , Dept. of Computer Science, University of North Carolina-Chapel Hill, USA
Montek Singh , Dept. of Computer Science, University of North Carolina-Chapel Hill, USA
pp. 409-416

LMS-based low-complexity game workload prediction for DVFS (PDF)

Benedikt Dietrich , Institute for Real-Time Computer Systems, TU Munich, Germany
Swaroop Nunna , Institute for Real-Time Computer Systems, TU Munich, Germany
Dip Goswami , Institute for Real-Time Computer Systems, TU Munich, Germany
Samarjit Chakraborty , Institute for Real-Time Computer Systems, TU Munich, Germany
Matthias Gries , Intel Labs, Braunschweig, Germany
pp. 417-424

Exploiting SIMD extensions for linear image processing with OpenCL (PDF)

Samuel Antao , Instituto Superior Técnico/INESC-ID, Technical University of Lisbon, Portugal
Leonel Sousa , Instituto Superior Técnico/INESC-ID, Technical University of Lisbon, Portugal
pp. 425-430

A co-processor approach for accelerating data-structure intensive algorithms (PDF)

Jason Loew , SUNY Binghamton Computer Science Department, USA
Jesse Elwell , SUNY Binghamton Computer Science Department, USA
Dmitry Ponomarev , SUNY Binghamton Computer Science Department, USA
Patrick H. Madden , SUNY Binghamton Computer Science Department, USA
pp. 431-438

SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS (PDF)

Tushar Krishna , Department of EECS, Massachusetts Institute of Technology, USA
Jacob Postman , School of EECS, Oregon State University, USA
Christopher Edmonds , School of EECS, Oregon State University, USA
Li-Shiuan Peh , Department of EECS, Massachusetts Institute of Technology, USA
Patrick Chiang , School of EECS, Oregon State University, USA
pp. 439-446

A fine-grained link-level fault-tolerant mechanism for networks-on-chip (PDF)

Arseniy Vitkovskiy , Dept. of Electrical Engineering and Information Technology, Cyprus University of Technology, 3036 Limassol, Cyprus
Vassos Soteriou , Dept. of Electrical Engineering and Information Technology, Cyprus University of Technology, 3036 Limassol, Cyprus
Chrysostomos Nicopoulos , Department of Electrical and Computer Engineering, University of Cyprus, 1678 Nicosia, Cyprus
pp. 447-454

Bandwidth optimization in asynchronous NoCs by customizing link wire length (PDF)

Junbok You , Electrical and Computer Engineering, University of Utah, USA
Daniel Gebhardt , School of Computing, University of Utah, USA
Kenneth S. Stevens , Electrical and Computer Engineering, University of Utah, USA
pp. 455-461

A high performance router with dynamic buffer allocation for on-chip interconnect networks (PDF)

Shubo Qi , School of Computer Science, National University of Defense Technology, Changsha, Hunan, China
Minxuan Zhang , School of Computer Science, National University of Defense Technology, Changsha, Hunan, China
Jinwen Li , School of Computer Science, National University of Defense Technology, Changsha, Hunan, China
Tianlei Zhao , School of Computer Science, National University of Defense Technology, Changsha, Hunan, China
Chengyi Zhang , School of Computer Science, National University of Defense Technology, Changsha, Hunan, China
Shaoqing Li , School of Computer Science, National University of Defense Technology, Changsha, Hunan, China
pp. 462-467

DDPSL: An easy way of defining properties (PDF)

Luigi Di Guglielmo , Dipartimento di Informatica - Università di Verona, Italy
Franco Fummi , Dipartimento di Informatica - Università di Verona, Italy
Nicola Orlandi , Dipartimento di Informatica - Università di Verona, Italy
Graziano Pravadelli , Dipartimento di Informatica - Università di Verona, Italy
pp. 468-473

DfT optimization for pre-bond testing of 3D-SICs containing TSVs (PDF)

Jia Li , School of Software, Tsinghua University, Beijing, China
Dong Xiang , School of Software, Tsinghua University, Beijing, China
pp. 474-479

Efficient test response compaction for robust BIST using parity sequences (PDF)

Thomas Indlekofer , Computer Engineering Group, University of Paderborn, Germany
Michael Schnittger , Computer Engineering Group, University of Paderborn, Germany
Sybille Hellebrand , Computer Engineering Group, University of Paderborn, Germany
pp. 480-485

EQUIPE: Parallel equivalence checking with GP-GPUs (PDF)

Debapriya Chatterjee , Department of Computer Science and Engineering, University of Michigan, USA
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan, USA
pp. 486-493

Identifying optimal generic processors for biomedical implants (PDF)

Christos Strydis , Computer Engineering Laboratory, Electrical Engineering Dept., Delft University of Technology, Postbus 5031, 2600 GA, The Netherlands
Dhara Dave , Computer Engineering Laboratory, Electrical Engineering Dept., Delft University of Technology, Postbus 5031, 2600 GA, The Netherlands
pp. 494-501

Exploiting application-dependent ambient temperature for accurate architectural simulation (PDF)

Hyung Beom Jang , Division of Computer and Communication Engineering, Korea University, Seoul, Korea
Jinhang Choi , Division of Computer and Communication Engineering, Korea University, Seoul, Korea
Ikroh Yoon , Department of Mechanical Engineering, Hongik University, Seoul, Korea
Sung-Soo Lim , College of Electrical Engineering and Computer Science, Kookmin University, Seoul, Korea
Seungwon Shin , Department of Mechanical Engineering, Hongik University, Seoul, Korea
Naehyuck Chang , School of Computer Science and Engineering, Seoul National University, Korea
Sung Woo Chung , Division of Computer and Communication Engineering, Korea University, Seoul, Korea
pp. 502-508

Inter-socket victim cacheing for platform power reduction (PDF)

Subhra Mazumdar , University of California, San Diego, USA
Dean M. Tullsen , University of California, San Diego, USA
Justin Song , Intel Corporation, USA
pp. 509-514

Dynamic register file partitioning in superscalar microprocessors for energy efficiency (PDF)

Meltem Ozsoy , State University of New York - Binghamton, USA
Y. Onur Kocberber , EPFL - Parallel Systems Architecture Lab (PARSA), Switzerland
Mehmet Kayaalp , State University of New York - Binghamton, USA
Oguz Ergin , TOBB University of Economics and Technology, Turkey
pp. 515-520

Package-Aware Scheduling of embedded workloads for temperature and Energy management on heterogeneous MPSoCs (PDF)

Shervin Sharifi , Computer Science and Engineering Department, University of California, San Diego, USA
Tajana Simunic Rosing , Computer Science and Engineering Department, University of California, San Diego, USA
pp. 521-527

Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability (PDF)

Yu Liu , Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA
Kaijie Wu , Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA
pp. 528-533

IP characterization methodology for fast and accurate power consumption estimation at transactional level model (PDF)

Michel Rogers-Vallee , Microelectronics Research Group, École Polytechnique of Montréal, Canada
Marc-Andre Cantin , Digital Department, MDA Space corporation, Sainte-Anne-de-Bellevue, Canada
Laurent Moss , Microelectronics Research Group, École Polytechnique of Montréal, Canada
Guy Bois , Microelectronics Research Group, École Polytechnique of Montréal, Canada
pp. 534-541

Enhancing dual-Vt design with consideration of on-chip temperature variation (PDF)

Junjun Gu , University of Maryland, College Park, 20742, USA
Gang Qu , University of Maryland, College Park, 20742, USA
Lin Yuan , Synopsys Inc., Mountain View, CA 94043, USA
pp. 542-547

BDD-based circuit restructuring for reducing dynamic power (PDF)

Quang Dinh , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Deming Chen , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Martin D. F. Wong , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
pp. 548-554
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