The Community for Technology Leaders
2009 IEEE International Conference on Computer Design (2009)
Lake Tahoe, CA USA
Oct. 4, 2009 to Oct. 7, 2009
ISSN: 1063-6404
ISBN: 978-1-4244-5029-9
TABLE OF CONTENTS

Imperfection-immune Carbon Nanotube digital VLSI (PDF)

Nishant Patil , Department of Electrical Engineering and Department of Computer Science, Stanford University, Stanford, CA
Subhasish Mitra , Department of Electrical Engineering and Department of Computer Science, Stanford University, Stanford, CA
pp. 1

Computer-aided design for microfluidic chips based on multilayer soft lithography (PDF)

Nada Amin , Massachusetts Institute of Technology
William Thies , Microsoft Research India
Saman Amarasinghe , Massachusetts Institute of Technology
pp. 2-9

Automatic synthesis of computation interference constraints for relative timing verification (PDF)

Yang Xu , Electrical and Computer Engineering Department, University of Utah
Kenneth S. Stevens , Electrical and Computer Engineering Department, University of Utah
pp. 16-22

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations (PDF)

Renshen Wang , Department of Computer Science and Engineering, University of California, San Diego La Jolla, CA 92093-0404
Takumi Okamoto , System IP Core Research Lab NEC Corporation Kawasaki, Kanagawa 211-8666, Japan
Chung-Kuan Cheng , Department of Computer Science and Engineering University of California, San Diego La Jolla, CA 92093-0404
pp. 23-28

Statistical timing analysis based on simulation of lithographic process (PDF)

Aswin Sreedhar , University of Massachusetts at Amherst
Sandip Kundu , University of Massachusetts at Amherst
pp. 29-34

Compiler-directed leakage reduction in embedded microprocessors (PDF)

Soumyaroop Roy , Department of Computer Science and Engineering University of South Florida Tampa, FL 33620
Nagarajan Ranganathan , Department of Computer Science and Engineering University of South Florida Tampa, FL 33620
Srinivas Katkoori , Department of Computer Science and Engineering University of South Florida Tampa, FL 33620
pp. 35-40

Efficient calibration of thermal models based on application behavior (PDF)

Youngwoo Ahn , Texas A&M University
Inchoon Yeo , Texas A&M University
Riccardo Bettati , Texas A&M University
pp. 41-46

Using checksum to reduce power consumption of display systems for low-motion content (PDF)

Kyungtae Han , Intel Labs, Hillsboro, OR 97124
Zhen Fang , Intel Labs, Hillsboro, OR 97124
Paul Diefenbaugh , Intel Labs, Hillsboro, OR 97124
Richard Forand , Intel Labs, Hillsboro, OR 97124
Ravi R. Iyer , Intel Labs, Hillsboro, OR 97124
Donald Newell , Intel Labs, Hillsboro, OR 97124
pp. 47-53

A disruptive computer design idea: Architectures with repeatable timing (PDF)

Stephen A. Edwards , Columbia University
Sungjun Kim , Columbia University
Edward A. Lee , UC Berkeley
Isaac Liu , UC Berkeley
Hiren D. Patel , UC Berkeley
Martin Schoeberl , Vienna University of Technology
pp. 54-59

Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer's workflow add-on? (PDF)

Uzi Vishkin , University of Maryland Institute for Advanced Computer Studies (Umiacs)
pp. 60-63

Quality improvement and cost reduction using statistical outlier methods (PDF)

Amit Nahar , Texas Instruments, Dallas, TX
Kenneth M. Butler , Texas Instruments, Dallas, TX
John M. Carulli , Texas Instruments, Dallas, TX
Charles Weinberger , Texas Instruments, Dallas, TX
pp. 64-69

Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs (PDF)

Brandon Noia , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708
Yuan Xie , Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802
pp. 70-77

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study (PDF)

Matthieu Dubois , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Salvador Mir , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
pp. 78-83

Design and test strategies for microarchitectural post-fabrication tuning (PDF)

Xiaoyao Liang , Suzhou University
Benjamin C. Lee , Stanford University
Gu-Yeon Wei , Harvard University
David Brooks , Harvard University
pp. 84-90

Impact analysis of performance faults in modern microprocessors (PDF)

Naghmeh Karimi , ECE Department University of Tehran
Michail Maniatakos , EE Department Yale University
Chandra Tirumurti , Strategic CAD Labs Intel Corporation
Abhijit Jas , Validation and Test Solutions Intel Corporation
Yiorgos Makris , EE Department Yale University
pp. 91-96

A robust pulsed flip-flop and its use in enhanced scan design (PDF)

Rajesh Kumar , Department of ECE, Texas A&M University, College Station TX 77843
Kalyana C. Bollapalli , Department of ECE, Texas A&M University, College Station TX 77843
Rajesh Garg , Intel Corporation, Hillsboro, OR 97124
Tarun Soni , Department of ECE, Texas A&M University, College Station TX 77843
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843
pp. 97-102

Enabling resonant clock distribution with scaled on-chip magnetic inductors (PDF)

Saurabh Sinha , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
Wei Xu , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
Jyothi B. Velamala , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
Tawab Dastagir , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
Bertan Bakkaloglu , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
Hongbin Yu , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
Yu Cao , Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706
pp. 103-108

A flexible communication scheme for rationally-related clock frequencies (PDF)

Jean-Michel Chabloz , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm
Ahmed Hemani , Department of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Stockholm
pp. 109-116

VariPipe: Low-overhead variable-clock synchronous pipelines (PDF)

Navid Toosizadeh , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
Safwat G. Zaky , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
Jianwen Zhu , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
pp. 117-124

N-way ring and square arbiters (PDF)

Masashi Imai , The University of Tokyo
Tomohiro Yoneda , National Institute of Informatics
Takashi Nanya , The University of Tokyo
pp. 125-130

On-chip bidirectional wiring for heavily pipelined systems using network coding (PDF)

Kalyana C. Bollapalli , Department of ECE, Texas A&M University, College Station TX 77843
Rajesh Garg , Intel Corporation, Hillsboro, OR 97124
Kanupriya Gulati , Department of ECE, Texas A&M University, College Station TX 77843
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843
pp. 131-136

WHOLE: A low energy I-Cache with separate way history (PDF)

Zichao Xie , Microprocessor Research & Development Center, Peking University, Beijing, China
Dong Tong , Microprocessor Research & Development Center, Peking University, Beijing, China
Xu Cheng , Microprocessor Research & Development Center, Peking University, Beijing, China
pp. 137-143

Reducing dynamic power dissipation in pipelined forwarding engines (PDF)

Weirong Jiang , Ming Hsieh Department of Electrical Engineering University of Southern California, Los Angeles, CA 90089, USA
Viktor K. Prasanna , Ming Hsieh Department of Electrical Engineering University of Southern California, Los Angeles, CA 90089, USA
pp. 144-149

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery (Abstract)

S. Petit , Department of Computer Engineering (DISCA) Universidad Politécnica de Valencia, Spain
R. Ubal , Department of Computer Engineering (DISCA) Universidad Politécnica de Valencia, Spain
J. Sahuquillo , Department of Computer Engineering (DISCA) Universidad Politécnica de Valencia, Spain
P. Lopez , Department of Computer Engineering (DISCA) Universidad Politécnica de Valencia, Spain
pp. 150-157

Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design (PDF)

Hai Lin , Dept. of Electrical & Computer Engineering University of Connecticut. Storrs, CT 06269
Yunsi Fei , Dept. of Electrical & Computer Engineering University of Connecticut. Storrs, CT 06269
pp. 158-165

Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors (PDF)

Nasir Mohyuddin , Department of Electrical Engineering (Systems) University of Southern California, Los Angeles, CA, USA
Kimish Patel , Department of Electrical Engineering (Systems) University of Southern California, Los Angeles, CA, USA
Massoud Pedram , Department of Electrical Engineering (Systems) University of Southern California, Los Angeles, CA, USA
pp. 166-172

Real-time, unobtrusive, and efficient program execution tracing with stream caches and last stream predictors (Abstract)

Vladimir Uzelac , ECE Department, The University of Alabama in Huntsville
Aleksandar Milenkovic , IBM, Austin, Texas
Milena Milenkovic , IBM, Austin, Texas
Martin Burtscher , ICES, The University of Texas at Austin
pp. 173-178

Transaction-based debugging of system-on-chips with patterns (PDF)

Amir Masoud Gharehbaghi , VLSI Design and Education Center, University of Tokyo, Tokyo, Japan
Masahiro Fujita , VLSI Design and Education Center, University of Tokyo, Tokyo, Japan
pp. 186-192

A new verification method for embedded systems (PDF)

Robert A. Thacker , University of Utah
Chris J. Myers , University of Utah
Kevin Jones , University of Utah
Scott R. Little , Freescale Semiconductor, Inc
pp. 193-200

A hierarchical approach towards system level static timing verification of SoCs (PDF)

Rupsa Chakraborty , Department of Computer Science and Engineering Indian Institute of Technology Kharagpur, India - 721302
Dipanwita Roy Chowdhury , Department of Computer Science and Engineering Indian Institute of Technology Kharagpur, India - 721302
pp. 201-206

Timing variation-aware high-level synthesis considering accurate yield computation (PDF)

Jongyoon Jung , School of Electrical Engineering and Computer Science, Seoul National University, Korea
Taewhan Kim , School of Electrical Engineering and Computer Science, Seoul National University, Korea
pp. 207-212

Fault-tolerant synthesis using non-uniform redundancy (PDF)

Keven L. Woo , Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064
Matthew R. Guthaus , Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064
pp. 213-218

Low-overhead error detection for Networks-on-Chip (PDF)

Amit Berman , Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000, Israel
Idit Keidar , Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000, Israel
pp. 219-224

3D stacked power distribution considering substrate coupling (PDF)

Amirali Shayan , University of California, San Diego
Xiang Hu , University of California, San Diego
Wanping Zhang , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
A. Ege Engin , San Diego State University
Xiaoming Chen , Qualcomm, Inc
Mikhail Popovich , Qualcomm, Inc
pp. 225-230

Interconnect performance corners considering crosstalk noise (PDF)

Ravikishore Gandikota , EECS, University of Michigan
David Blaauw , EECS, University of Michigan
Dennis Sylvester , EECS, University of Michigan
pp. 231-237

Reducing register file size through instruction pre-execution enhanced by value prediction (PDF)

Yusuke Tanaka , Department of Computational Science and Engineering Nagoya University
Hideki Ando , Department of Electrical Engineering and Computer Science Nagoya University
pp. 238-245

Reusing cached schedules in an out-of-order processor with in-order issue logic (PDF)

Oscar Palomar , Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya
Toni JuanJ , Intel® Corporation
Juan J. Navarro , Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya
pp. 246-253

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis (PDF)

Ahmed Al Maashri , Department of Computer Science and Engineering, Penn State University
Guangyu Sun , Department of Computer Science and Engineering, Penn State University
Xiangyu Dong , Department of Computer Science and Engineering, Penn State University
Vijay Narayanan , Department of Computer Science and Engineering, Penn State University
Yuan Xie , Department of Computer Science and Engineering, Penn State University
pp. 254-259

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies (PDF)

Cheng-Kok Koh , School of Electrical and Computer Engineering, Purdue University
Weng-Fai Wong , Dept. of Computer Science, National Univ of Singapore
Yiran Chen , Seagate Technologies
Hai Li , Dept. of Electrical and Computer Engineering, Polytechnic Institute of NYU
pp. 268-274

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors (Abstract)

Javier Lira , Universitat Politècnica de Catalunya
Carlos Molina , Universitat Politècnica de Catalunya
Antonio Gonzalez , Intel Barcelona Research Center, Intel Labs - UPC
pp. 275-281

Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling (PDF)

Jiayuan Meng , Department of Computer Science, University of Virginia
Kevin Skadron , Department of Computer Science, University of Virginia
pp. 282-288

SHIELDSTRAP: Making secure processors truly secure (PDF)

Siddhartha Chhabra , North Carolina State University
Brian Rogers , North Carolina State University
Yan Solihin , North Carolina State University
pp. 289-296

Rapid early-stage microarchitecture design using predictive models (PDF)

Christophe Dubach , Members of HiPEAC School of Informatics, University of Edinburgh, UK
Timothy M. Jones , Members of HiPEAC School of Informatics, University of Edinburgh, UK
Michael F.P. O'Boyle , Members of HiPEAC School of Informatics, University of Edinburgh, UK
pp. 297-304

Efficient binary translation system with low hardware cost (PDF)

Weiwu Hu , Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Qi Liu , Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Jian Wang , Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Songsong Cai , Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Menghao Su , Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaoyu Li , Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 305-312

Defect-based test optimization for analog/RF circuits for near-zero DPPM applications (PDF)

Ender Yilmaz , Arizona State University
Sule Ozev , Arizona State University
pp. 313-318

Iterative built-in testing and tuning of mixed-signal/RF systems (PDF)

H. Choi , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
A. Chatterjee , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
V. Natarajan , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
S. Devarakond , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
S. Sen , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
D. Han , Texas Instruments, Dallas, TX, USA
R. Senguttuvan , Texas Instruments, Dallas, TX, USA
S. Bhattacharya , Texas Instruments, Dallas, TX, USA
A. Goyal , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
D. Lee , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
M. Swaminathan , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, USA
pp. 319-326

Testing bio-chips (PDF)

Krishnendu Chakrabarty , Duke University
pp. 327

Online multiple error detection in crossbar nano-architectures (PDF)

Navid Farazmand , Department of Electrical and Computer Engineering Northeastern University, Boston, MA
Mehdi B. Tahoori , Department of Electrical and Computer Engineering Northeastern University, Boston, MA
pp. 335-342

Adaptive online testing for efficient hard fault detection (PDF)

Shantanu Gupta , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor
Amin Ansari , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor
Shuguang Feng , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor
Scott Mahlke , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor
pp. 343-349

FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing (PDF)

Chun-Yi Lee , Dept. of Electrical Engineering, Princeton University, Princeton, NJ 08544
Niraj K. Jha , Dept. of Electrical Engineering, Princeton University, Princeton, NJ 08544
pp. 350-357

Analysis and optimization of pausible clocking based GALS design (Abstract)

Xin Fan , IHP Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Milos Krstic , IHP Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Eckhard Grass , IHP Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
pp. 358-365

Reliable cache design with detection of gate oxide breakdown using BIST (PDF)

Fahad Ahmed , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
Linda Milor , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
pp. 366-371

Efficient architectures for elliptic curve cryptography processors for RFID (PDF)

Lawrence Leinweber , Case Western Reserve University
Christos Papachristou , Case Western Reserve University
Francis G. Wolff , Case Western Reserve University
pp. 372-377

Multiplier-less and table-less linear approximation for square and square-root (PDF)

In-Cheol Park , Division of Electrical Engineering, Korea Advanced Institute of Science and Technology
Tae-Hwan Kim , Division of Electrical Engineering, Korea Advanced Institute of Science and Technology
pp. 378-383

On improving the algorithmic robustness of a low-power FIR filter (PDF)

Sourabh Khire , Georgia Institute of Technology, Atlanta, GA 30332
Saibal Mukhopadhyay , Georgia Institute of Technology, Atlanta, GA 30332
pp. 384-389

Pragmatic design of gated-diode FinFET DRAMs (PDF)

Ajay N. Bhoj , Dept. of Electrical Engineering Princeton University, Princeton, NJ 08544
Niraj K. Jha , Dept. of Electrical Engineering Princeton University, Princeton, NJ 08544
pp. 390-397

Empirical performance models for 3T1D memories (PDF)

Kristen Lovin , Microsoft Corporation
Benjamin C. Lee , Stanford University
Xiaoyao Liang , Suzhou University
David Brooks , Harvard University
Gu-Yeon Wei , Harvard University
pp. 398-403

ColSpace: Towards algorithm/implementation co-optimization (PDF)

Jiawei Huang , Department of Electrical and Computer Engineering University of Virginia
John Lach , Department of Electrical and Computer Engineering University of Virginia
pp. 404-411

A novel SoC architecture on FPGA for ultra fast face detection (PDF)

Chun He , Research Institute of Electronic Science & Tech., Univ. of Electronic Science & Technology of China
Alexandros Papakonstantinou , Electrical & Computer Eng. Dept., Univ. of Illinois, Urbana-Champaign, IL, USA
Deming Chen , Electrical & Computer Eng. Dept., Univ. of Illinois, Urbana-Champaign, IL, USA
pp. 412-418

Optical lithography simulation using wavelet transform (PDF)

Rance Rodrigues , University of Massachusetts at Amherst
Aswin Sreedhar , University of Massachusetts at Amherst
Sandip Kundu , University of Massachusetts at Amherst
pp. 427-432

Computational bit-width allocation for operations in vector calculus (PDF)

Adam B. Kinsman , Department of Electrical and Computer Engineering McMaster University, Hamilton, ON L8S4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering McMaster University, Hamilton, ON L8S4K1, Canada
pp. 433-438

Topology-driven cell layout migration with collinear constraints (PDF)

De-Shiun Fu , Computer Science Department National Chiao Tung University Hsin-Chu 300, Taiwan
Ying-Zhih Chaung , Computer Science Department National Chiao Tung University Hsin-Chu 300, Taiwan
Yen-Hung Lin , Computer Science Department National Chiao Tung University Hsin-Chu 300, Taiwan
Yih-Lang Li , Computer Science Department National Chiao Tung University Hsin-Chu 300, Taiwan
pp. 439-444

A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips (PDF)

Tsung-Wei Huang , Department of Computer Science and Information Engineering National Cheng Kung University, Tainan, Taiwan
Tsung-Yi Ho , Department of Computer Science and Information Engineering National Cheng Kung University, Tainan, Taiwan
pp. 445-450

Accurate estimation of vector dependent leakage power in the presence of process variations (PDF)

Romana Fernandes , University of Cincinnati, Cincinnati, OH, USA
Ranga Vemuri , University of Cincinnati, Cincinnati, OH, USA
pp. 451-458

Code density concerns for new architectures (PDF)

Vincent M. Weaver , Cornell University
Sally A. McKee , Chalmers University of Technology
pp. 459-464

Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions (PDF)

J. Michael Anderson , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
Charles Tsen , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
Liang-Kai Wang , Advanced Micro Devices, Inc
Katherine Compton , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
J. Michael Schulte , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
pp. 465-471

The impact of liquid cooling on 3D multi-core processors (PDF)

Hyung Beom Jang , Division of Computer and Communication Engineering, Korea University, Seoul, Korea
Ikroh Yoon , Department of Mechanical Engineering, Hongik University, Seoul, Korea
Cheol Hong Kim , School of Electronics and Computer Engineering, Chonnam National University, Gwangu, Korea
Seungwon Shin , Department of Mechanical Engineering, Hongik University, Seoul, Korea
Sung Woo Chung , Division of Computer and Communication Engineering, Korea University, Seoul, Korea
pp. 472-478

Intra-vector SIMD instructions for core specialization (PDF)

Cor Meenderinck , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, Delft, The Netherlands
Ben Juurlink , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, Delft, The Netherlands
pp. 479-484

A high throughput FFT processor with no multipliers (PDF)

Shakeel S. Abdullah , Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712, USA
Haewoon Nam , Mobile Devices Technology Office, Motorola Inc, Austin, TX 78730, USA
Mark McDermot , Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712, USA
Jacob A. Abraham , Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712, USA
pp. 485-490

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design (PDF)

Mateja Putic , University of Virginia
Liang Di , Intel Corporation
Benton H. Calhoun , University of Virginia
John Lach , University of Virginia
pp. 491-497

A radiation tolerant Phase Locked Loop design for digital electronics (PDF)

Rajesh Kumar , Department of ECE, Texas A&M University, College Station TX 77843
Vinay Karkala , Department of ECE, Texas A&M University, College Station TX 77843
Rajesh Garg , Intel Corporation, Hillsboro, OR 97124
Tanuj Jindal , Department of ECE, Texas A&M University, College Station TX 77843
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843
pp. 505-510

A PLL design based on a standing wave resonant oscillator (PDF)

Vinay Karkala , Department of ECE, Texas A&M University, College Station TX 77843
Kalyana C. Bollapalli , Department of ECE, Texas A&M University, College Station TX 77843
Rajesh Garg , Intel Corporation, Hillsboro, OR 97124
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station TX 77843
pp. 511-516

Mid-range wireless energy transfer using inductive resonance for wireless sensors (PDF)

Shahrzad Jalali Mazlouman , Simon Fraser University
Alireza Mahanfar , Simon Fraser University
Bozena Kaminska , Simon Fraser University
pp. 517-522

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes (PDF)

Satyanand Nalam , University of Virgnia
Mudit Bhargava , Carnegie Mellon University
Kyle Ringgenberg , University of Virgnia
Ken Mai , Carnegie Mellon University
Benton H. Calhoun , University of Virgnia
pp. 523-528
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