The Community for Technology Leaders
2008 IEEE International Conference on Computer Design (2008)
Lake Tahoe, CA USA
Oct. 12, 2008 to Oct. 15, 2008
ISSN: 1063-6404
ISBN: 978-1-4244-2657-7
TABLE OF CONTENTS

Fault tolerant Four-State Logic by using Self-Healing Cells (PDF)

Thomas Panhofer , Austrian Aerospace GmbH, Austria
Werner Friesenbichler , Austrian Aerospace GmbH, Austria
Martin Delvai , Institute of Computer Engineering, Vienna University of Technology, Austria
pp. 1-6

Probabilistic error propagation in logic circuits using the Boolean difference calculus (PDF)

Nasir Mohyuddin , University of Southern California, Department of Electrical Engineering, Los Angeles, USA
Ehsan Pakbaznia , University of Southern California, Department of Electrical Engineering, Los Angeles, USA
Massoud Pedram , University of Southern California, Department of Electrical Engineering, Los Angeles, USA
pp. 7-13

A novel, highly SEU tolerant digital circuit design approach (PDF)

Rajesh Garg , Department of ECE, Texas A&M University, College Station 77843, USA
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station 77843, USA
pp. 14-20

Power-state-aware buffered tree construction (PDF)

Iris Hui-Ru Jiang , Dept of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan
Ming-Hua Wu , Realtek Semiconductor Corp., Hsinchu Science Park, 300, Taiwan
pp. 21-26

A parallel Steiner tree heuristic for macro cell routing (PDF)

Christian Fobel , Deptartment of Computing and Information Science, University of Guelph, Ontario, Canada, N1G 2W1
Gary Grewal , Deptartment of Computing and Information Science, University of Guelph, Ontario, Canada, N1G 2W1
pp. 27-33

Configurable rectilinear Steiner tree construction for SoC and nano technologies (PDF)

Iris Hui-Ru Jiang , Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan
Yen-Ting Yu , Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan
pp. 34-39

Improving SAT-based Combinational Equivalence Checking through circuit preprocessing (PDF)

Fabricio Vivas Andrade , Computer Science Department, Centro Federal de Educação Tecnológica, de Minas Gerais, Brazil
Leandro M. Silva , Computer Science Department, Universidade Federal de Minas Gerais, Brazil
Antonio O. Fernandes , Computer Science Department, Universidade Federal de Minas Gerais, Brazil
pp. 40-45

Ant Colony Optimization directed program abstraction for software bounded model checking (PDF)

Xueqi Cheng , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
pp. 46-51

Propositional approximations for bounded model checking of partial circuit designs (PDF)

Bernd Becker , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
Marc Herbstritt , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
Natalia Kalinnik , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
Matthew Lewis , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
Juri Lichtner , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
Tobias Nopper , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
Ralf Wimmer , Albert-Ludwigs-University, Freiburg im Breisgau, Germany
pp. 52-59

Energy-precision tradeoffs in mobile Graphics Processing Units (PDF)

Jeff Pool , Dept. of Computer Science, University of North Carolina-Chapel Hill, USA
Anselmo Lastra , Dept. of Computer Science, University of North Carolina-Chapel Hill, USA
Montek Singh , Dept. of Computer Science, University of North Carolina-Chapel Hill, USA
pp. 60-67

Dynamically reconfigurable soft output MIMO detector (PDF)

Pankaj Bhagawat , Dept. of E.C.E, Texas A&M University, College-Station, TX-77840, USA
Rajballav Dash , Dept. of E.C.E, Texas A&M University, College-Station, TX-77840, USA
Gwan Choi , Dept. of E.C.E, Texas A&M University, College-Station, TX-77840, USA
pp. 68-73

Applying speculation techniques to implement functional units (PDF)

Alberto A. Del Barrio , Dpto. Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain
Maria C. Molina , Dpto. Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain
Jose M. Mendias , Dpto. Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain
Esther Andres , Dpto. Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain
Roman Hermida , Dpto. Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain
Francisco Tirado , Dpto. Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain
pp. 74-80

Accelerating search and recognition with a TCAM functional unit (PDF)

Atif Hashmi , Department of Electrical and Computer Engineering, University of Wisconsin - Madison, USA
Mikko Lipasti , Department of Electrical and Computer Engineering, University of Wisconsin - Madison, USA
pp. 81-86

Improved combined binary/decimal fixed-point multipliers (PDF)

Brian Hickmann , University of Wisconsin - Madison, Dept. of Electrical and Computer Engineering, 53706, USA
Michael Schulte , University of Wisconsin - Madison, Dept. of Electrical and Computer Engineering, 53706, USA
Mark Erle , International Business Machines, 6677 Sauterne Drive, Macungie, PA 18062, USA
pp. 87-94

Architecture implementation of an improved decimal CORDIC method (PDF)

Jose-Luis Sanchez , Computer Technology Department, University of Alicante, Spain
Higinio Mora , Computer Technology Department, University of Alicante, Spain
Jeronimo Mora , Computer Technology Department, University of Alicante, Spain
Antonio Jimeno , Computer Technology Department, University of Alicante, Spain
pp. 95-100

A study of reliability issues in clock distribution networks (PDF)

Aida Todri , UCSB, ECE Department, USA
Malgorzata Marek-Sadowska , UCSB, ECE Department, USA
pp. 101-106

Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations (PDF)

ChunChen Liu , Electrical and Computer Engineering Department, University of California, San Diego, USA
Junjie Su , Electrical and Computer Engineering Department, University of California, San Diego, USA
Yiyu Shi , Electrical Engineering Department, University of California, Los Angeles, USA
pp. 107-113

Custom rotary clock router (PDF)

Vinayak Honkote , Electrical and Computer Engineering, Drexel University, Philadelphia, USA
Baris Taskin , Electrical and Computer Engineering, Drexel University, Philadelphia, USA
pp. 114-119

Safe clocking register assignment in datapath synthesis (PDF)

Keisuke Inoue , Japan Advanced Institute of Science and Technology, Japan
Mineo Kaneko , Japan Advanced Institute of Science and Technology, Japan
Tsuyoshi Iwagaki , Japan Advanced Institute of Science and Technology, Japan
pp. 120-127

Gate planning during placement for gated clock network (PDF)

Weixiang Shen , EDA Lab, Dept.of Computer Science and Technology, Tsinghua University, Beijing, 100084, China
Yici Cai , EDA Lab, Dept.of Computer Science and Technology, Tsinghua University, Beijing, 100084, China
Xianlong Hong , EDA Lab, Dept.of Computer Science and Technology, Tsinghua University, Beijing, 100084, China
Jiang Hu , Dept.of Electrical and Computer Engineering, Texas A&M University, College Station, 77843, USA
pp. 128-133

Near-optimal oblivious routing on three-dimensional mesh networks (PDF)

Rohit Sunkam Ramanujam , University of California, San Diego, La Jolla, 92093-0407 USA
Bill Lin , University of California, San Diego, La Jolla, 92093-0407 USA
pp. 134-141

Design of application-specific 3D Networks-on-Chip architectures (PDF)

Shan Yan , Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, 92093-0407, USA
Bill Lin , Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, 92093-0407, USA
pp. 142-149

Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic (PDF)

Ahmad Khonsari , ECE Department, University of Tehran, School of Computer Science, IPM, Iran
Mohammad R. Aghajani , School of Computer Science, IPM, Iran
Arash Tavakkol , School of Computer Science, IPM, Iran
Mohammad S. Talebi , School of Computer Science, IPM, Iran
pp. 150-155

A resource efficient content inspection system for next generation Smart NICs (PDF)

Karthikeyan Sabhanatarajan , HCS Research Lab, ECE Department, University of Florida, USA
Ann Gordon-Ross , HCS Research Lab, ECE Department, University of Florida, USA
pp. 156-163

Contention-aware application mapping for Network-on-Chip communication architectures (PDF)

Chen-Ling Chou , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
Radu Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
pp. 164-169

Adaptive SRAM memory for low power and high yield (PDF)

Baker Mohammad , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Stephen Bijansky , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Adnan Aziz , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Jacob Abraham , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
pp. 176-181

On-chip high performance signaling using passive compensation (PDF)

Yulei Zhang , University of California, San Diego, La Jolla, 92093-0404, USA
Ling Zhang , University of California, San Diego, La Jolla, 92093-0404, USA
Akira Tsuchiya , Kyoto University, 606-8501, JAPAN
Masanori Hashimoto , Osaka University, Suita, 565-0871, JAPAN
Chung-Kuan Cheng , University of California, San Diego, La Jolla, 92093-0404, USA
pp. 182-187

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters (PDF)

Michael Pehl , Institute for Electronic Design Automation, Technische Universitït München, Department for Electrical Engineering and Information Technology, Arcisstr. 21, 80 333 Munich, Germany
Tobias Massier , Institute for Electronic Design Automation, Technische Universitït München, Department for Electrical Engineering and Information Technology, Arcisstr. 21, 80 333 Munich, Germany
Helmut Graeb , Institute for Electronic Design Automation, Technische Universitït München, Department for Electrical Engineering and Information Technology, Arcisstr. 21, 80 333 Munich, Germany
Ulf Schlichtmann , Institute for Electronic Design Automation, Technische Universitït München, Department for Electrical Engineering and Information Technology, Arcisstr. 21, 80 333 Munich, Germany
pp. 188-193

Characterization and design of sequential circuit elements to combat soft error (PDF)

Hamed Abrishami , University of Southern California, Department of Electrical Engineering, Los Angeles, 90089, USA
Safar Hatami , University of Southern California, Department of Electrical Engineering, Los Angeles, 90089, USA
Massoud Pedram , University of Southern California, Department of Electrical Engineering, Los Angeles, 90089, USA
pp. 194-199

Comparative analysis of NBTI effects on low power and high performance flip-flops (PDF)

K. Ramakrishnan , Microsystems Design Laboratory (MDL), Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
X. Wu , Microsystems Design Laboratory (MDL), Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
N. Vijaykrishnan , Microsystems Design Laboratory (MDL), Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
Y. Xie , Microsystems Design Laboratory (MDL), Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
pp. 200-205

In-field NoC-based SoC testing with distributed test vector storage (PDF)

Jason D. Lee , Texas A&M University, USA
Rabi N. Mahapatra , Texas A&M University, USA
pp. 206-211

Test-access mechanism optimization for core-based three-dimensional SOCs (PDF)

Xiaoxia Wu , Computer Science and Engineering Department, The Pennsylvania State University, University Park, 16802, USA
Yibo Chen , Computer Science and Engineering Department, The Pennsylvania State University, University Park, 16802, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Yuan Xie , Computer Science and Engineering Department, The Pennsylvania State University, University Park, 16802, USA
pp. 212-218

Characterization of granularity and redundancy for SRAMs for optimal yield-per-area (PDF)

Jae Chul Cha , Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
Sandeep K. Gupta , Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
pp. 219-226

Dynamic test scheduling for analog circuits for improved test quality (PDF)

Ender Yilmaz , Department of Electrical Engineering, Arizona State University, USA
Sule Ozev , Department of Electrical Engineering, Arizona State University, USA
pp. 227-233

Test cost minimization through adaptive test development (PDF)

Mingjing Chen , CSE Department, UC San Diego, La Jolla, CA 92093, USA
Alex Orailoglu , CSE Department, UC San Diego, La Jolla, CA 92093, USA
pp. 234-239

Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA (PDF)

Yong Dou , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, ChangSha, China, 410073
Fei Xia , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, ChangSha, China, 410073
Xingming Zhou , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, ChangSha, China, 410073
Xuejun Yang , National Laboratory for Parallel&Distributed Processing, National University of Defense Technology, ChangSha, China, 410073
pp. 240-247

A high-performance parallel CAVLC encoder on a fine-grained many-core system (PDF)

Zhibin Xiao , ECE Department, University of California, Davis, USA
Bevan Baas , ECE Department, University of California, Davis, USA
pp. 248-254

Acceleration of a 3D target tracking algorithm using an application specific instruction set processor (PDF)

Sebastien Fontaine , Department of Computer and Software Engineering, École Polytechnique de Montréal, Canada
Sylvain Goyette , Department of Computer and Software Engineering, École Polytechnique de Montréal, Canada
J.M. Pierre Langlois , Department of Computer and Software Engineering, École Polytechnique de Montréal, Canada
Guy Bois , Department of Computer and Software Engineering, École Polytechnique de Montréal, Canada
pp. 255-259

Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs (PDF)

Amir Hossein Gholamipour , Donald Bren School of Information and Computer Science, University of California, Irvine, USA
Elaheh Bozorgzadeh , Donald Bren School of Information and Computer Science, University of California, Irvine, USA
Lichun Bao , Donald Bren School of Information and Computer Science, University of California, Irvine, USA
pp. 260-265

Application Specific Instruction set processor specialized for block motion estimation (PDF)

Marc-Andre Daigneault , Groupe de recherche en microélectronique et microsystèmes, École Polytechnique de Montréal, Canada
J.M. Pierre Langlois , Groupe de recherche en microélectronique et microsystèmes, École Polytechnique de Montréal, Canada
Jean Pierre David , Groupe de recherche en microélectronique et microsystèmes, École Polytechnique de Montréal, Canada
pp. 266-271

Prototyping a hybrid main memory using a virtual machine monitor (PDF)

Dong Ye , Northeastern University, USA
Aravind Pavuluri , VMware, Inc., USA
Carl A. Waldspurger , VMware, Inc., USA
Brian Tsang , Rambus, Inc., USA
Bohuslav Rychlik , Rambus, Inc., USA
Steven Woo , Rambus, Inc., USA
pp. 272-279

Variation-aware thermal characterization and management of multi-core architectures (PDF)

Eren Kursun , IBM Thomas J. Watson Research Center, Yorktown Heights, USA
Chen-Yong Cher , IBM Thomas J. Watson Research Center, Yorktown Heights, USA
pp. 280-285

Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective (PDF)

Venkatesan Packirisamy , University of Minnesota, Minneapolis, USA
Yangchun Luo , University of Minnesota, Minneapolis, USA
Wei-Lung Hung , University of Minnesota, Minneapolis, USA
Antonia Zhai , University of Minnesota, Minneapolis, USA
Pen-Chung Yew , University of Minnesota, Minneapolis, USA
Tin-Fook Ngai , Intel Corporation, USA
pp. 286-293

Analysis and minimization of practical energy in 45nm subthreshold logic circuits (PDF)

David Bol , Microelectronics laboratory, Université catholique de Louvain, Belgium
Renaud Ambroise , Microelectronics laboratory, Université catholique de Louvain, Belgium
Denis Flandre , Microelectronics laboratory, Université catholique de Louvain, Belgium
Jean-Didier Legat , Microelectronics laboratory, Université catholique de Louvain, Belgium
pp. 294-300

Power-aware soft error hardening via selective voltage scaling (PDF)

Kai-Chiang Wu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
Diana Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
pp. 301-306

Reversi: Post-silicon validation system for modern microprocessors (PDF)

Ilya Wagner , University of Michigan, USA
Valeria Bertacco , University of Michigan, USA
pp. 307-314

Digital filter synthesis considering multiple adder graphs for a coefficient (PDF)

Jeong-Ho Han , School of EECS, Korea Advanced Institute of Science and Technology, Daejeon, Korea
In-Cheol Park , School of EECS, Korea Advanced Institute of Science and Technology, Daejeon, Korea
pp. 315-320

A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications (PDF)

Adnan Suleiman , Cirrus Logic, USA
Hani Saleh , Intel Corporation, USA
Adel Hussein , University of Texas at San Antonio, Electrical and Computer Engineering Department, USA
David Akopian , University of Texas at San Antonio, Electrical and Computer Engineering Department, USA
pp. 321-327

Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264 (PDF)

Zhenyu Liu , The Graduate School of IPS, Waseda University, Japan
Satoshi Goto , The Graduate School of IPS, Waseda University, Japan
Takeshi Ikenaga , The Graduate School of IPS, Waseda University, Japan
pp. 328-333

Highly reliable A/D converter using analog voting (PDF)

A. Namazi , Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, 75083, USA
S. Askari , Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, 75083, USA
M. Nourani , Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, 75083, USA
pp. 334-339

Hierarchical simulation-based verification of Anton, a special-purpose parallel machine (PDF)

Stanley C. Wang , D. E. Shaw Research, New York, 10036, USA
J.P. Grossman , D. E. Shaw Research, New York, 10036, USA
C. Richard Ho , D. E. Shaw Research, New York, 10036, USA
Douglas J. Ierardi , D. E. Shaw Research, New York, 10036, USA
Brian Towles , D. E. Shaw Research, New York, 10036, USA
Brannon Batson , D. E. Shaw Research, New York, 10036, USA
Jochen Spengler , D. E. Shaw Research, New York, 10036, USA
John K. Salmon , D. E. Shaw Research, New York, 10036, USA
Rolf Mueller , D. E. Shaw Research, New York, 10036, USA
Michael Theobald , D. E. Shaw Research, New York, 10036, USA
Cliff Young , D. E. Shaw Research, New York, 10036, USA
Joseph Gagliardo , D. E. Shaw Research, New York, 10036, USA
Martin M. Deneroff , D. E. Shaw Research, New York, 10036, USA
Ron O. Dror , D. E. Shaw Research, New York, 10036, USA
David E. Shaw , D. E. Shaw Research, New York, 10036, USA
pp. 340-347

Post-silicon verification for cache coherence (PDF)

Andrew DeOrio , Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Adam Bauserman , Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Valeria Bertacco , Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
pp. 348-355

Acquiring an exhaustive, continuous and real-time trace from SoCs (PDF)

Christian Hochberger , Department of Computer Science, Dresden University of Technology, Germany
Alexander Weiss , Accemic GmbH & Co. KG, Flintsbach, Germany
pp. 356-362

CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework (PDF)

Andrea Pellegrini , University of Michigan, USA
Kypros Constantinides , University of Michigan, USA
Dan Zhang , University of Michigan, USA
Shobana Sudhakar , University of Michigan, USA
Valeria Bertacco , University of Michigan, USA
Todd Austin , University of Michigan, USA
pp. 363-370

Exploiting spare resources of in-order SMT processors executing hard real-time threads (PDF)

Jorg Mische , University of Augsburg, Germany
Sascha Uhrig , University of Augsburg, Germany
Florian Kluge , University of Augsburg, Germany
Theo Ungerer , University of Augsburg, Germany
pp. 371-376

Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design (PDF)

Carsten Gremzow , Faculty of Computer Science and Electrical Engineering, Berlin University of Technology, Germany
pp. 377-383

A simple latency tolerant processor (PDF)

Satyanarayana Nekkalapu , Electrical and Computer Engineering, American University of Beirut, Lebanon
Haitham Akkary , Electrical and Computer Engineering, American University of Beirut, Lebanon
Komal Jothi , Electrical and Computer Engineering, Portland State University, USA
Renjith Retnamma , Electrical and Computer Engineering, Portland State University, USA
Xiaoyu Song , Electrical and Computer Engineering, Portland State University, USA
pp. 384-389

Low-cost open-page prefetch scheduling in chip multiprocessors (PDF)

Marius Grannaes , Norwegian University of Science and Technology, HiPEAC European Network of Excellence, Norway
Magnus Jahre , Norwegian University of Science and Technology, HiPEAC European Network of Excellence, Norway
Lasse Natvig , Norwegian University of Science and Technology, HiPEAC European Network of Excellence, Norway
pp. 390-396

Simulation points for SPEC CPU 2006 (PDF)

Arun A. Nair , Dept. of Electrical and Computer Engineering, University of Texas at Austin, 78712 USA
Lizy K. John , Dept. of Electrical and Computer Engineering, University of Texas at Austin, 78712 USA
pp. 397-403

Synthesis of parallel prefix adders considering switching activities (PDF)

Taeko Matsunaga , Graduate School of Information, Production and Systems, Waseda University, Japan
Shinji Kimura , Graduate School of Information, Production and Systems, Waseda University, Japan
Yusuke Matsunaga , Faculty of Information Science and Electrical Engineering, Kyushu University, Japan
pp. 404-409

Conversion driven design of binary to mixed radix circuits (PDF)

Ashur Rafiev , School of Electrical, Electronic & Computer Engineering, Newcastle University, UK
Julian P. Murphy , School of Electrical, Electronic & Computer Engineering, Newcastle University, UK
Danil Sokolov , School of Electrical, Electronic & Computer Engineering, Newcastle University, UK
Alex Yakovlev , School of Electrical, Electronic & Computer Engineering, Newcastle University, UK
pp. 410-415

Systematic design of high-radix Montgomery multipliers for RSA processors (PDF)

Atsushi Miyamoto , Graduate School of Information Sciences, Tohoku University, Japan
Naofumi Homma , Graduate School of Information Sciences, Tohoku University, Japan
Takafumi Aoki , Graduate School of Information Sciences, Tohoku University, Japan
Akashi Satoh , Research Center for Information Security, AIST, Japan
pp. 416-421

An improved micro-architecture for function approximation using piecewise quadratic interpolation (PDF)

Shai Erez , School of Electrical Engineering, Tel-Aviv University, Israel
Guy Even , School of Electrical Engineering, Tel-Aviv University, Israel
pp. 422-426

A floating-point fused dot-product unit (PDF)

Hani H. Saleh , Intel Corporation, 5000 Plaza on the Lake Blvd., Austin, TX 78746, USA
Earl E. Swartzlander , ECE Department, University of Texas at Austin, USA
pp. 427-431

Chip level thermal profile estimation using on-chip temperature sensors (PDF)

Yufu Zhang , University of Maryland, USA
Ankur Srivastava , University of Maryland, USA
Mohamed Zahran , City University of New York, USA
pp. 432-437

Early stage FPGA interconnect leakage power estimation (PDF)

Shilpa Bhoj , Center for Integrated Circuits and Systems, The University of Texas at Dallas, Richardson, USA
Dinesh Bhatia , Center for Integrated Circuits and Systems, The University of Texas at Dallas, Richardson, USA
pp. 438-443

Modeling and analysis of non-rectangular transistors caused by lithographic distortions (PDF)

Aswin Sreedhar , Electrical and Computer Engineering, University of Massachusetts at Amherst, USA
Sandip Kundu , Electrical and Computer Engineering, University of Massachusetts at Amherst, USA
pp. 444-449

A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions (PDF)

Dimitris Bountas , University of Thessaly, Department of Computer and Communication Engineering Volos, 38221, Greece
Georgios Stamoulis , University of Thessaly, Department of Computer and Communication Engineering Volos, 38221, Greece
Nestoras Evmorfopoulos , University of Thessaly, Department of Computer and Communication Engineering Volos, 38221, Greece
pp. 450-456

Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield (PDF)

Aditya Bansal , IBM T. J. Watson Research, Yorktown Heights, NY, USA
Rama N. Singh , IBM T. J. Watson Research, Yorktown Heights, NY, USA
Saibal Mukhopadhyay , Georgia Institute of Technology, Atlanta, USA
Geng Han , IBM Microelectronics, SRDC, Hopewell Junction, NY, USA
Fook-Luen Heng , IBM T. J. Watson Research, Yorktown Heights, NY, USA
Ching-Te Chuang , National Chiao Tung University, Hsinchu, Taiwan
pp. 457-462

Frequency and voltage planning for multi-core processors under thermal constraints (PDF)

Michael Kadin , Division of Engineering, Brown University Providence, RI 02912, USA
Sherief Reda , Division of Engineering, Brown University Providence, RI 02912, USA
pp. 463-470

Understanding performance, power and energy behavior in asymmetric multiprocessors (PDF)

Nagesh B. Lakshminarayana , School of Computer Science, Georgia Institute of Technology, USA
Hyesoon Kim , School of Computer Science, Georgia Institute of Technology, USA
pp. 471-477

Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor (PDF)

Michael Gschwind , IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
pp. 478-485

The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks (PDF)

Reza Sabbaghi-Nadooshan , Central Tehran & Science and Research Branch, Islamic Azad University, Iran
Mehdi Modarressi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Hamid Sarbazi-Azad , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 486-490

Design and evaluation of an optical CPU-DRAM interconnect (PDF)

Amit Hadke , Department of Electrical & Computer Engineering, University of California, Davis, 95616 USA
Tony Benavides , Department of Computer Science, University of California, Davis, 95616 USA
Rajeevan Amirtharajah , Department of Computer Science, University of California, Davis, 95616 USA
Matthew Farrens , Department of Electrical & Computer Engineering, University of California, Davis, 95616 USA
Venkatesh Akella , Department of Computer Science, University of California, Davis, 95616 USA
pp. 492-497

Leveraging speculative architectures for run-time program validation (PDF)

Juan Carlos Martinez Santos , Dept. of Electrical and Computer Engineering, University of Connecticut, USA
Yunsi Fei , Dept. of Electrical and Computer Engineering, University of Connecticut, USA
pp. 498-505

Bridging the gap between nanomagnetic devices and circuits (PDF)

Michael Niemier , Department of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
X. Sharon Hu , Department of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
Aaron Dingler , Department of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
M. Tanvir Alam , Department of Electrical Engineering, University of Notre Dame, IN 46556, USA
G. Bernstein , Department of Electrical Engineering, University of Notre Dame, IN 46556, USA
W. Porod , Department of Electrical Engineering, University of Notre Dame, IN 46556, USA
pp. 506-513

Techniques for increasing effective data bandwidth (PDF)

Christopher Nitta , University of California, Davis, USA
Matthew Farrens , University of California, Davis, USA
pp. 514-519

RMA: A Read Miss-Based Spin-Down Algorithm using an NV Cache (PDF)

Hyotaek Shim , Computer Science Department at KAIST, Korea
Jaegeuk Kim , Computer Science Department at KAIST, Korea
Dawoon Jung , Computer Science Department at KAIST, Korea
Jin-Soo Kim , Computer Science Department at KAIST, Korea
Seungryoul Maeng , Computer Science Department at KAIST, Korea
pp. 520-525

Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes (PDF)

Jiangli Zhu , Case Western Reserve University, USA
Xinmiao Zhang , Case Western Reserve University, USA
Zhongfeng Wang , Broadcom Corporation, USA
pp. 526-531

Timing analysis considering IR drop waveforms in power gating designs (PDF)

Shih-Hung Weng , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Yu-Min Kuo , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Malgorzata Marek-Sadowska , Department of ECE, University of California, Santa Barbara, USA
pp. 532-537

A dynamic accuracy-refinement approach to timing-driven technology mapping (PDF)

Sz-Cheng Huang , Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan
Jie-Hong R. Jiang , Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan
pp. 538-543

Modeling and reduction of complex timing constraints in high performance digital circuits (PDF)

Nagbhushan Veerapaneni , Google, Mountain View, CA USA
C.Y. Roger Chen , Dept. of EECS, Syracuse University, NY USA
pp. 544-550

SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement (PDF)

Anuj Kumar , Department of Electrical and Computer Engineering, University of Wisconsin, Madison 53706 USA
Tai-Hsuan Wu , Department of Electrical and Computer Engineering, University of Wisconsin, Madison 53706 USA
Azadeh Davoodi , Department of Electrical and Computer Engineering, University of Wisconsin, Madison 53706 USA
pp. 551-556

Is there always performance overhead for regular fabric? (PDF)

Yi-Wei Lin , UC Santa Barbara, USA
Malgorzata Marek-Sadowska , UC Santa Barbara, USA
Wojciech Maly , Carnegie Mellon University, USA
Andrzej Pfitzner , Warsaw University of Technology, Poland
Dominik Kasprowicz , Warsaw University of Technology, Poland
pp. 557-562

Adaptive techniques for leakage power management in L2 cache peripheral circuits (PDF)

Houman Homayoun , Department of Computer Science, UC Irvine, USA
Alex Veidenbaum , Department of Computer Science, UC Irvine, USA
Jean-Luc Gaudiot , Department of Electrical and Computer Engineering, UC Irvine, USA
pp. 563-569

Energy-aware opcode design (PDF)

Balaji V. Iyer , School of Computer Science, College of Computing, Georgia Institute of Technology, Atlanta, USA
Jason A. Poovey , Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, USA
Thomas M. Conte , School of Computer Science, College of Computing, Georgia Institute of Technology, Atlanta, USA
pp. 570-576

Making register file resistant to power analysis attacks (PDF)

Shuo Wang , University of Connecticut, Storrs, 06269, USA
Fan Zhang , University of Connecticut, Storrs, 06269, USA
Jianwei Dai , University of Connecticut, Storrs, 06269, USA
Lei Wang , University of Connecticut, Storrs, 06269, USA
Zhijie Jerry Shi , University of Connecticut, Storrs, 06269, USA
pp. 577-582

Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads (PDF)

Shrirang Yardi , The Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061. USA
Michael S. Hsiao , The Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061. USA
pp. 583-590

Suitable cache organizations for a novel biomedical implant processor (PDF)

Christos Strydis , Computer Engineering Lab, Delft University of Technology, P.O. Box 5031, 2600 GA, The Netherlands
pp. 591-598

Issue system protection mechanisms (PDF)

Pedro Chaparro , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Spain
Jaume Abella , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Spain
Javier Carretero , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Spain
Xavier Vera , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Spain
pp. 599-604

Power switch characterization for fine-grained dynamic voltage scaling (PDF)

Liang Di , Intel Corporation, USA
Mateja Putic , University of Virginia, USA
John Lach , University of Virginia, USA
Benton H. Calhoun , University of Virginia, USA
pp. 605-611

A fine-grain dynamic sleep control scheme in MIPS R3000 (PDF)

Seidai Takeda , Shibaura Institute of Technology, Japan
Naomi Seki , Keio University, Japan
Jo Kei , Keio University, Japan
Daisuke Ikebuchi , Keio University, Japan
Yu Kojima , Keio University, Japan
Yohei Hasegawa , Keio University, Japan
Hideharu Amano , Keio University, Japan
Toshihiro Kashima , Shibaura Institute of Technology, Japan
Lei Zhao , Keio University, Japan
Toshiaki Shirai , Shibaura Institute of Technology, Japan
Mitustaka Nakata , Shibaura Institute of Technology, Japan
Kimiyoshi Usami , Shibaura Institute of Technology, Japan
Tetsuya Sunata , Tokyo University of Agriculture and Technology, Japan
Jun Kanai , Tokyo University of Agriculture and Technology, Japan
Mitaro Namiki , Tokyo University of Agriculture and Technology, Japan
Masaaki Kondo , The University of Electro-Communications, Japan
Hiroshi Nakamura , The University of Tokyo, Japan
pp. 612-617

Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW (PDF)

Hao Xu , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030 USA
Ranga Vemuri , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030 USA
Wen-Ben Jone , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030 USA
pp. 618-625

Energy-delay tradeoffs in 32-bit static shifter designs (PDF)

Steven Huntzicker , Harvey Mudd College, Claremont, CA 91711 USA
Michael Dayringer , Harvey Mudd College, Claremont, CA 91711 USA
Justin Soprano , Harvey Mudd College, Claremont, CA 91711 USA
Anthony Weerasinghe , Harvey Mudd College, Claremont, CA 91711 USA
David Money Harris , Harvey Mudd College, Claremont, CA 91711 USA
Dinesh Patil , Sun Microsystems Laboratories, USA
pp. 626-632

Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems (PDF)

Baoxian Zhao , Department of Computer Science, George Mason University, Fairfax, VA 22030 USA
Hakan Aydin , Department of Computer Science, George Mason University, Fairfax, VA 22030 USA
Dakai Zhu , Department of Computer Science, University of Texas at San Antonio, 78249 USA
pp. 633-639

Router and cell library co-development for improving redundant via insertion at pins (PDF)

Wei-Chih Tseng , Computer Science and Engineering, Yuan Ze University, Chung-Li, 320 Taiwan
Yu-Hsing Chen , Computer Science and Engineering, Yuan Ze University, Chung-Li, 320 Taiwan
Rung-Bin Lin , Computer Science and Engineering, Yuan Ze University, Chung-Li, 320 Taiwan
pp. 646-651

ECO-Map: Technology remapping for post-mask ECO using simulated annealing (PDF)

Nilesh A. Modi , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106 USA
Malgorzata Marek-Sadowska , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106 USA
pp. 652-657

Global bus route optimization with application to microarchitectural design exploration (PDF)

Dae Hyun Kim , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Sung Kyu Lim , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
pp. 658-663

Fast arbiters for on-chip network switches (PDF)

Giorgos Dimitrakopoulos , Institute of Computer Science (ICS), Foundation for Research and Technology - Hellas (FORTH), FORTH-ICS, 100 Plastira Ave, Heraklion, Crete GR-70-013 Greece
Nikos Chrysos , Institute of Computer Science (ICS), Foundation for Research and Technology - Hellas (FORTH), FORTH-ICS, 100 Plastira Ave, Heraklion, Crete GR-70-013 Greece
Kostas Galanopoulos , Computer Engineering and Informatics Dept., University of Patras, 26500, Greece
pp. 664-670

Re-examining cache replacement policies (PDF)

Jason Zebchuk , Dept. of Electrical and Computer Engineering, University of Toronto, Canada
Srihari Makineni , Systems Technology Lab, Intel Corporation, USA
Don Newell , Systems Technology Lab, Intel Corporation, USA
pp. 671-678

Two dimensional highly associative level-two cache design (PDF)

Chuanjun Zhang , Department of Computer Science and Electrical Engineering, University of Missouri-Kansas City, USA
Bing Xue , Department of Computer Science and Electrical Engineering, University of Missouri-Kansas City, USA
pp. 679-684

Exploiting producer patterns and L2 cache for timely dependence-based prefetching (PDF)

Chungsoo Lim , North Carolina State University, USA
Gregory T. Byrd , North Carolina State University, USA
pp. 685-692

Ring data location prediction scheme for Non-Uniform Cache Architectures (PDF)

Sayaka Akioka , Waseda University, Japan
Feihui Li , NVIDIA, USA
Konrad Malkowski , The Pennsylvania State University, USA
Padma Raghavan , The Pennsylvania State University, USA
Mahmut Kandemir , The Pennsylvania State University, USA
Mary Jane Irwin , The Pennsylvania State University, USA
pp. 693-698

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits (PDF)

Houman Homayoun , Department of Computer Science, UC Irvine, USA
Mohammad Makhzan , Department of Electrical and Computer Engineering, UC Irvine, USA
Alex Veidenbaum , Department of Computer Science, UC Irvine, USA
pp. 699-706
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