The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (2005)
San Jose, California
Oct. 2, 2005 to Oct. 5, 2005
ISBN: 0-7695-2451-6
TABLE OF CONTENTS
Introduction
9.1 Low Power Circuit Architecture (II)
Cover
Introduction
Keynote Presentation

Latency Lags Bandwidth (PDF)

Professor David Patterson , University of California at Berkeley
pp. 3-6
1.1 Power and Thermal Consideration in Processor Design (I)

Temperature-Dependent Optimization of Cache Leakage Power Dissipation (Abstract)

Peng Li , Department of EE, Texas A&M University
Lawrence T. Pileggi , Department of ECE, Carnegie Mellon University
Yangdong Deng , Incentia Design Systems, Santa Clara, CA
pp. 7-12

Architectural Considerations for Energy Efficiency (Abstract)

Bart R. Zeydel , Advanced Computer Systems Engineering Laboratory Department of Electrical and Computer Engineering, University of California, Davis, CA
Vojin G. Oklobdija , Advanced Computer Systems Engineering Laboratory Department of Electrical and Computer Engineering, University of California, Davis, CA
Hoang Q. Dao , Advanced Computer Systems Engineering Laboratory Department of Electrical and Computer Engineering, University of California, Davis, CA
pp. 13-16

Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines (Abstract)

Anahita Shayesteh , Computer Science Department, University of California, Los Angeles
Glenn Reinman , Computer Science Department, University of California, Los Angeles
Suleyman Sair , Department of Electrical and Computer Engineering, North Carolina State University
Tim Sherwood , Computer Science Department, University of California, Santa Barbara
Eren Kursun , Computer Science Department, University of California, Los Angeles
pp. 17-23

Analytical Model for Sensor Placement on Microprocessors (Abstract)

Kevin Skadron , Departments of Computer Science, and Electrical and Computer Engineering, University of Virginia
Kyeong-Jae Lee , Departments of Computer Science, and Electrical and Computer Engineering, University of Virginia
Wei Huang , Departments of Computer Science, and Electrical and Computer Engineering, University of Virginia
pp. 24-30
1.2 Interconnect Prediction and Optimization

Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages (Abstract)

Zion Shen , Cadence Design Systems 555 River Oaks Parkway, San Jose, CA
Chris C.N. Chu , Cadence Design Systems 555 River Oaks Parkway, San Jose, CA
Ying-Meng Li , Atoptech, Inc. 2700 Augustine Drive Santa Clara
pp. 38-44

X-Routing using Two Manhattan Route Instances (Abstract)

Sunil P Khatri , Department of CS, Texas A&M University, College Station TX 77843
Seraj Ahmad , Department of CS, Texas A&M University, College Station TX 77843
Edward Hursey , Department of ECE, University of Colorado, Boulder, CO 80303
Vijay Balasubramanian , Department of CS, Texas A&M University, College Station TX 77843
Rabi Mahapatra , Department of CS, Texas A&M University, College Station TX 77843
Nikhil Jayakumar , Department of EE, Texas A&M University, College Station TX 77843
pp. 45-52
1.3 System-Level Architecture

Hardware Support for Bulk Data Movement in Server Platforms (Abstract)

Srihari Makineni , Communications Technology Lab, Intel Corporation, Hillsboro, OR
Li Zhao , Department of Computer Science and Engineering, University of California, Riverside, CA
Laxmi Bhuyan , Department of Computer Science and Engineering, University of California, Riverside, CA
Don Newell , Communications Technology Lab, Intel Corporation, Hillsboro, OR
Ravi Iyer , Communications Technology Lab, Intel Corporation, Hillsboro, OR
pp. 53-60

Counter-Based Cache Replacement Algorithms (Abstract)

Mazen Kharbutli , Department of Electrical and Computer Engineering, North Carolina State University
Yan Solihin , Department of Electrical and Computer Engineering, North Carolina State University
pp. 61-68

Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths (Abstract)

Bita Gorjiara , Center for Embedded Computer Systems (CECS), University of California Irvine
Daniel Gajski , Center for Embedded Computer Systems (CECS), University of California Irvine
Mehrdad Reshadi , Center for Embedded Computer Systems (CECS), University of California Irvine
pp. 69-76
Panel Discussion

Are Today?s Verification Tools Able to Handle Current Design Challenges? (PDF)

Stuart Swwan , Cadence Design Systems
Harry Foster , Jasper DA
Rich Faris , Marketing Director RealIntent
Ken Larsen , Mentor Graphics
pp. 77
2.1 Power aware System Design

Energy-Efficient Color Approximation for Digital LCD Interfaces (Abstract)

Enrico Macii , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
Sabino Salerno , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
Massimo Poncino , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
Andi Nourrachmat , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
pp. 81-86

Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms (Abstract)

Davide Bertozzi , University of Ferrara, via Saragat, 1 - Ferrara, Italy
Andrea Acquaviva , University of Urbino, STI, Piazza Repubblica, 13 - Urbino, Italy
Luca Benini , University of Bologna, DEIS, Viale Risorgimento, 2 - Bologna, Italy
Martino Ruggiero , University of Bologna, DEIS, Viale Risorgimento, 2 - Bologna, Italy
pp. 87-93

LCD Display Energy Reduction by User Monitoring (Abstract)

Vasily G. Moshnyaga , Department of Electronics Engineering and Computer Science, Fukuoka University, Japan
Eiji Morikawa , Department of Electronics Engineering and Computer Science, Fukuoka University, Japan
pp. 94-97

Frame Buffer Energy Optimization by Pixel Prediction (Abstract)

K. Patel , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
M. Poncino , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
E. Macii , Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY
pp. 98-101

Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System (PDF)

Wei Qin , ECE Department, Boston University MA
Ingrid Verbauwhede , EE Dept. UCLA, CA and ESAT, K.U.Leuven, BE
Bo-Cheng Charles Lai , EE Department, UCLA
Patrick Schaumont , ECE Department, Virginia Tech.
pp. 102-104

Near-memory Caching for Improved Energy Consumption (Abstract)

Daniel Mosse , Department of Computer Science, University of Pittsburgh
Nevine AbouGhazaleh , Department of Computer Science, University of Pittsburgh
Bruce Childers , Department of Computer Science, University of Pittsburgh
Rami Melhem , Department of Computer Science, University of Pittsburgh
pp. 105-110
2.2 Physical-Aware System-Level Analysis and Synthesis

Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz (Abstract)

Yuanfang Hu , Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Chung-Kuan Cheng , Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Yi Zhu , Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Hongyu Chen , Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Andrew A. Chien , Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
pp. 111-118

A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management (PDF)

Shrirang Yardi , Bradley Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA, USA.
Dong S. Ha , Bradley Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA, USA.
Karthik Channakeshava , Bradley Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA, USA.
Thomas L. Martin , Bradley Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA, USA.
Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA, USA.
pp. 119-126

Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study (Abstract)

Soheil Ghiasi , Department of Electrical and Computer Engineering University of California, Davis
pp. 127-129

EFFICIENT THERMAL SIMULATION FOR RUN-TIME TEMPERATURE TRACKING AND MANAGEMENT (Abstract)

Hang Li , Micron Technology Inc., San Jose, CA 95131
Jun Yang , Department of Computer Science and Engineering, University of California, Riverside, CA
Zhenyu Qi , Department of Electrical Engineering, University of California, Riverside, CA
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California, Riverside, CA
Wei Wu , Department of Computer Science and Engineering, University of California, Riverside, CA
Lingling Jin , Department of Computer Science and Engineering, University of California, Riverside, CA
Pu Liu , Department of Electrical Engineering, University of California, Riverside, CA
pp. 130-136
2.3 SoC Test Methods

A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs (Abstract)

Sule Ozev , Department of Electrical & Computer Engineering Duke University, Durham, NC.
Anuja Sehgal , Department of Electrical & Computer Engineering Duke University, Durham, NC.
Krishnendu Chakrabarty , Department of Electrical & Computer Engineering Duke University, Durham, NC.
pp. 137-142

Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree (Abstract)

Hideo Ito , Faculty of Engineering, Chiba University, Japan
Gang Zeng , Graduate School of Science and Technology, Chiba University, Japan
pp. 143-146

ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values (Abstract)

Seongmoon Wang , NEC Labs. America, Princeton, NJ
Kwang-Ting Cheng , Dept. of ECE, UC-Santa Barbara, CA
Mango C.-T. Chao , Dept. of ECE, UC-Santa Barbara, CA
Srimat T. Chakradhar , NEC Labs. America, Princeton, NJ
pp. 147-152

Accurate Diagnosis of Multiple Faults (Abstract)

Yung-Chieh Lin , Dept. of ECE, University of California, Santa Barbara, Santa Barbara, USA
Kwang-Ting Cheng , Dept. of ECE, University of California, Santa Barbara, Santa Barbara, USA
Feng Lu , Dept. of ECE, University of California, Santa Barbara, Santa Barbara, USA
pp. 153-156

Quick Scan Chain Diagnosis Using Signal Profiling (Abstract)

Shi-Yu Huang , Department of Electrical Engineering, National Tsing-Hua University, Taiwan
Jheng-Syun Yang , Department of Electrical Engineering, National Tsing-Hua University, Taiwan
pp. 157-160

Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits (Abstract)

Fang Liu , Department of Electrical & Computer Engineering, Duke University
Sule Ozev , Department of Electrical & Computer Engineering, Duke University
pp. 161-170
3.1 Reliable Circuit Design

Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration (Abstract)

Song Peng , Computer Systems Laboratory, Cornell University, Ithaca, NY, USA
Rajit Manohar , Computer Systems Laboratory, Cornell University, Ithaca, NY, USA
pp. 171-179

Error-tolerance memory Microarchitecture via Dynamic Multithreading (Abstract)

Lei Wang , Dept. of Electrical and Computer Engineering University of Connecticut
pp. 179-184

A Soft Error Monitor Using Switching Current Detection (Abstract)

Qikai Chen , Dept. of ECE, Purdue University, West Lafayette, IN, USA
Kaushik Roy , Dept. of ECE, Purdue University, West Lafayette, IN, USA
Amit Agarwal , Dept. of ECE, Purdue University, West Lafayette, IN, USA
Patrick Ndai , Dept. of ECE, Purdue University, West Lafayette, IN, USA
pp. 185-192
3.2 High Level Systhersis

Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation (Abstract)

A. Chattopadhyay , Institute for Integrated Signal Processing Systems RWTH Aachen University, Aachen, Germany
O. Schliebusch , Institute for Integrated Signal Processing Systems RWTH Aachen University, Aachen, Germany
D. Kammler , Institute for Integrated Signal Processing Systems RWTH Aachen University, Aachen, Germany
E. M. Witte , Institute for Integrated Signal Processing Systems RWTH Aachen University, Aachen, Germany
pp. 193-199

Statistical Analysis Driven Synthesis of Asynchronous Systems (Abstract)

Mineo Kaneko , School of Information Science,Japan Advanced Institute of Science and Technology
Koji Ohashi , School of Information Science,Japan Advanced Institute of Science and Technology
pp. 200-205

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis (Abstract)

A. Raychowdhury , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
N. Banerjee , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
S. Bhunia , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
H. Mahmoodi , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
K. Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
pp. 206-214
3..3 Verification of SoCs with Datapaths and Software

Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths (Abstract)

Priyank Kalla , Department of Electrical and Computer Engineering University of Utah, Salt Lake City, UT
Florian Enescu , Department of Mathematics and Statistics Georgia State University, Atlanta, GA
Namrata Shekhar , Department of Electrical and Computer Engineering University of Utah, Salt Lake City, UT
Sivaram Gopalakrishnan , Department of Electrical and Computer Engineering University of Utah, Salt Lake City, UT
pp. 215-220

Incorporating Ef.cient Assertion Checkers into Hardware Emulation (Abstract)

Zeljko Zilic , McGill University,Montreal, Canada
Marc Boule , McGill University,Montreal, Canada
pp. 221-228

Assertion Checking of Behavioral Descriptions with Non-linear Solver (Abstract)

I. Ugarte , Microelectronics Engineering Group. TEISA Department. ETSIIT. University of Cantabria
P. Sanchez , Microelectronics Engineering Group. TEISA Department. ETSIIT. University of Cantabria
pp. 229-231

File System Interfaces for Embedded Software Development (Abstract)

Bhanu Pisupati , Indiana University Department of Computer Science
Geoffrey Brown , Indiana University Department of Computer Science
pp. 232-238
Keynote Address
4.1 Low Power Circuit Arhcitecture

Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines (Abstract)

Poras T. Balsara , Center for Integrated Circuits & Systems The University of Texas at Dallas Richardson, TX
Mehrdad Nourani , Center for Integrated Circuits & Systems The University of Texas at Dallas Richardson, TX
Mohammad J. Akhbarizadeh , Center for Integrated Circuits & Systems The University of Texas at Dallas Richardson, TX
Deepak S Vijayasarathi , Center for Integrated Circuits & Systems The University of Texas at Dallas Richardson, TX
pp. 243-248

Low- and Ultra Low-Power Arithmetic Units: Design and Comparison (Abstract)

Milena Vratonjic , Advanced Computer Systems Engineering Laboratory (ACSEL) University of California, Davis, CA
Vojin G. Oklobdzija , Advanced Computer Systems Engineering Laboratory (ACSEL) University of California, Davis, CA
Bart R. Zeydel , Advanced Computer Systems Engineering Laboratory (ACSEL) University of California, Davis, CA
pp. 249-252

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors (Abstract)

Yibin Ye , ECE Dept., Northwestern University, Evanston, IL, USA
Maged Ghoneima , ECE Dept., Northwestern University, Evanston, IL, USA
Muhammad Khellah , ECE Dept., Northwestern University, Evanston, IL, USA
James Tschanz , ECE Dept., Northwestern University, Evanston, IL, USA
Nasser Kurd , Circuits Research
Yehea Ismail , ECE Dept., Northwestern, University, Evanston, IL,
Srikanth Nimmagadda , LTD-Group, Intel, Hillsboro, OR
Javed Barkatullah , Circuits Research
pp. 253-257

Low-Power Design of 90-nm SuperH Processor Core (Abstract)

T oshihiro Hattori , Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan
Tetsuya Yamaday , Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
Yusuke Nitta , Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan
Kiwamu Tak ada , Hitachi ULSI systems CO., Ltd., 3-1-1, Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
Masahide Abe , Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan
Kenji Oguray , Hitachi ULSI systems CO., Ltd., 3-1-1, Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
Makoto Ishikawa , Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
Osamu Nishii , Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan
Fumio Arakawa , Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
Manabu Kusaoke , Hitachi ULSI systems CO., Ltd., 3-1-1, Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
Motokazu Ozawa , Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan
pp. 258-266
4.2 Emerging Design Styles and Applications

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow (Abstract)

Steven J.E. Wilton , Dept. of Electrical and Computer Engineering, University of British Columbia, Canada
Bradley R. Quinton , Dept. of Electrical and Computer Engineering, University of British Columbia, Canada
Mark R. Greenstreet , Dept. of Electrical and Computer Science, University of British Columbia, Canada
pp. 267-274

Algorithmic and Architectural Design Methodology for Particle Filters in Hardware (Abstract)

Rama Chellappa , Electrical and Computer Engineering Department, University of Maryland at College Park
Aswin C Sankaranarayanan , Electrical and Computer Engineering Department, University of Maryland at College Park
Ankur Srivastava , Electrical and Computer Engineering Department, University of Maryland at College Park
pp. 275-280

ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology (Abstract)

Wei Zhang , Department of Electrical Engineering, Princeton University, Princeton, NJ
Niraj K. Jha , Department of Electrical Engineering, Princeton University, Princeton, NJ
pp. 281-288

Automatic Synthesis of Composable Sequential Quantum Boolean Circuits (Abstract)

Li-Kai Chang , Department of Computer Science and Engineering, Tatung University Taipei, Taiwan
Fu-Chiung Cheng , Department of Computer Science and Engineering, Tatung University Taipei, Taiwan
pp. 289-296
4.3 Formal Verification - Form Hardware to Software (Invited)

Model Checking C Programs Using F-SOFT (Abstract)

Malay K. Ganai , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540
Aarti Gupta , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540
Franco Ivanicic , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540
Ilya Shlyakhter , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540
pp. 297-308

Dealing with I/O Devices in the Context of Pervasive System Verification (Abstract)

Wolfgang J. Paul , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Mark A. Hillebrand , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Thomas In der Rieden , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
pp. 309-316

Towards the Formal Verification of Lower System Layers in Automotive Systems (Abstract)

Tom In der Rieden , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Steffen Knapp , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Michael Gerke , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Sven Beyer , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Peter Bohm , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Wolfgang J. Paul , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Mark Hillebrand , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
Dirk Leinenbach , Saarland University, Dept. of Computer Science, 66123 Saarbrucken, Germany
pp. 317-326
5.1 Cache Memory Architecture

Restrictive Compression Techniques to Increase Level 1 Cache Capacity (Abstract)

Prateek Pujara , Dept of Electrical and Computer Engineering, Binghamton University Binghamton, NY
Aneesh Aggarwal , Dept of Electrical and Computer Engineering, Binghamton University Binghamton, NY
pp. 327-333

The TM3270 Media-Processor Data Cache (Abstract)

Stamatis Vassiliadis , Delft University of Technology Delft, The Netherlands
Jan-Willem van de Waerdt , Philips Semiconductors, San Jose, CA, USA
Hans van Antwerpen , Philips Semiconductors, San Jose, CA, USA
Jean-Paul van Itegem , Philips Semiconductors, San Jose, CA, USA
pp. 334-341

Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag (Abstract)

Masahiro Goshima , Graduate School of Information Science and Technology, The University of Tokyo, Tokyo, Bunkyo, Hongo, Japan
Luong D. Hung , Graduate School of Information Science and Technology, The University of Tokyo, Tokyo, Bunkyo, Hongo, Japan
Shuichi Sakai , Graduate School of Information Science and Technology, The University of Tokyo, Tokyo, Bunkyo, Hongo, Japan
pp. 342-350
5.2 Gate Timing abd Power Analysis

VGTA: Variation Aware Gate Timing Analysis (Abstract)

Massoud Pedram , Electrical Engineering Department, University of Southern California
Soroush Abbaspour , Electrical Engineering Department, University of Southern California
Hanif Fatemi , Electrical Engineering Department, University of Southern California
pp. 351-356

Exact lower bound for the number of switches in series to implement a combinational logic cell (Abstract)

F.R. Schneider , Instituto de Inform?tica - UFRGS CEP - Caixa Postal Porto Alegre - RS - Brasil
R.P. Ribas , Instituto de Inform?tica - UFRGS CEP - Caixa Postal Porto Alegre - RS - Brasil
A.I. Reis , Department of Electrical and Computer Engineering 200 Union Street SE, University of Minnesota, MN
S.S. Sapatnekar , Department of Electrical and Computer Engineering 200 Union Street SE, University of Minnesota, MN
pp. 357-362

A Waveform Independent Gate Model for Accurate Timing Analysis (Abstract)

Peng Li , Department of Electrical Engineering Texas A%M University, College Station, TX
Emrah Acar , IBM Austin Research Lab Austin, TX
pp. 363-365

Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis (Abstract)

Vishwani D. Agrawal , Dept. of ECE, Auburn University, Auburn, AL
Fei Hu , Dept. of ECE, Auburn University, Auburn, AL
pp. 366-372
5.3 Perform Modeling

Methods for Modeling Resource Contention on Simultaneous Multithreading Processors (Abstract)

Daniel A. Connors , Department of Electrical and Computer Engineering, University of Colorado Boulder, CO
Joshua L. Kihm , Department of Electrical and Computer Engineering, University of Colorado Boulder, CO
Tipp Moseley , Department of Computer Science University of Colorado Boulder, CO
Dirk Grunwald , Department of Computer Science University of Colorado Boulder, CO
pp. 373-380

Using Scratchpad to Exploit Object Locality in Java (Abstract)

Carl S. Lebsack , Department of Electrical and Computer Engineering Iowa State University Ames, IA
J. Morris Chang , Department of Electrical and Computer Engineering Iowa State University Ames, IA
pp. 381-386

Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture (Abstract)

Khaled Z. Ibrahim , Department of Electrical Engineering, Suez Canal University, Egypt.
pp. 387-392

Simulating Commercial Java Throughput Workloads: A Case Study (Abstract)

Lizy K. John , Department of Electrical and Comuputer Engineering, University of Texas at Austin
Yue Luo , Department of Electrical and Comuputer Engineering, University of Texas at Austin
pp. 393-398
6.1 Low Voltage Design

Minimum Energy Near-threshold Network of PLA based Design (Abstract)

Sunil P. Khatri , Department of Electrical Engineering, Texas A%M University, College Station, TX
Nikhil Jayakumar , Department of Electrical Engineering, Texas A%M University, College Station, TX
pp. 399-404

Robust Design of High Fan-In/Out Subthreshold Circuits (Abstract)

Lawrence T. Clark , Electrical Engineering Dept., Arizona State University, Tempe, AZ
Jinhui Chen , Electrical Engineering Dept., Arizona State University, Tempe, AZ
Yu Cao , Electrical Engineering Dept., Arizona State University, Tempe, AZ
pp. 405-410

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs (Abstract)

Navin Srivastava , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
Kaustav Banerjee , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
Sheng-Chih Lin , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
pp. 411-416

A Feasibility Study of Subthreshold SRAM Across Technology Generations (Abstract)

Kaushik Roy , Dept. of ECE, Purdue University, West Lafayette, IN
Arijit Raychowdhury , Dept. of ECE, Purdue University, West Lafayette, IN
Saibal Mukhopadhyay , Dept. of ECE, Purdue University, West Lafayette, IN
pp. 417-424
6.2 Physical-Aware Circuit Design

Variability-Driven Buffer Insertion Considering Correlations (Abstract)

Azadeh Davoodi , University of Maryland, College Park, MD
Ankur Srivastava , University of Maryland, College Park, MD
pp. 425-430

A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits (Abstract)

Elias Kougianos , Engineering Technology University of North Texas Denton, TX
Valmiki Mukherjee , Computer Science and Engineering University of North Texas Denton, TX
Saraju P. Mohanty , Computer Science and Engineering University of North Texas Denton, TX
pp. 431-437

Supply Voltage Degradation Aware Analytical Placement (Abstract)

Qinke Wang , Computer Science and Engineering Dept. Univ. of California, San Diego
Andrew B. Kahng , Computer Science and Engineering Dept. Univ. of California, San Diego
Bao Liu , Computer Science and Engineering Dept. Univ. of California, San Diego
pp. 437-443

Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners (Abstract)

Anuradha Agarwal , Department of ECECS, University of Cincinnati, Cincinnati, OH
Ranga Vemuri , Department of ECECS, University of Cincinnati, Cincinnati, OH
pp. 444-452
6.3 Verification and Test for Sequential Circuits and Delay Fault Models

Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults (PDF)

Manan Syal , Intel Corporation, Hillsboro, Oregon, US
Rajat Arora , Cadence Design Systems, San Jose, California, US
Michael S. Hsiao , Department of ECE, Virginia Tech Blacksburg, Virginia, US
pp. 453-460

Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core (Abstract)

Jacob A. Abraham , Computer Engineering Research CenterThe University of Texas at Austin Austin, TX, USA
Qiang Qiang , Electrical Engineering and Computer Science, Case Western Reserve University Cleveland, Ohio, USA
Qiang, Chia-Lun Chang , Electrical Engineering and Computer Science, Case Western Reserve University Cleveland, Ohio, USA
Daniel G. Saab , Electrical Engineering and Computer Science, Case Western Reserve University Cleveland, Ohio, USA
pp. 461-463

Towards finding path delay fault tests with high test efficiency using ZBDDs (Abstract)

Kyriakos Christou , ECE Dept.,University of Cyprus
Maria K. Michael , ECE Dept.,University of Cyprus
Spyros Tragoudas , Southern Illinois University
pp. 464-467

Quality Transition Fault Tests Suitable for Small Delay Defects (Abstract)

M.M. Vaseekar Kumar , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, IL
S. Tragoudas , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, IL
pp. 468-470

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals (Abstract)

N. Devtaprasanna , Department of ECE, University of Iowa, Iowa City, IA
A. Gunda , LSI Logic Corp., Milpitas, CA
S.M. Reddy , Department of ECE, University of Iowa, Iowa City, IA
I. Pomeranz , School of ECE, Purdue University, West Lafayette, IN
P. Krishnamurthy , LSI Logic Corp., Milpitas, CA 95035
pp. 471-474

At-Speed Logic BIST Architecture for Multi-Clock Designs (Abstract)

Jonhson Guo , SynTest Technologies, Inc., China
Laung-Terng Wang , SynTest Technologies, Inc.
Xiaoqing Wen , Kyushu Institute of Technology, Japan
Po-Ching Hsu , SynTest Technologies, Inc., Taiwan
Shianling Wu , SynTest Technologies, Inc.
pp. 475-478

Hardware Ef.cient LBISTWith Complementary Weights (Abstract)

Thomas Rinderknecht , Mentor Graphics Corp. Wilsonville, OR
Wu-Tung Cheng , Mentor Graphics Corp. Wilsonville, OR
Janak H. Patel , University of Illinois at Urbana-Champaign, Urbana, IL
Liyang Lai , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 479-484
7.1 New Memory Technologies (Invited)

FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance Applications (Abstract)

K. Boku , Texas Instruments, 13560 N. Central Expy, MS
Scott Summerfelt , Texas Instruments, 13560 N. Central Expy, MS
Edwin Jabillo , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO , USA
John Rodriquez , Texas Instruments, 13560 N. Central Expy, MS
John Gertas , Texas Instruments, 13560 N. Central Expy, MS-3736, Dallas, TX
Glen Fox , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO USA
K.R. Udayakumar , Texas Instruments, 13560 N. Central Expy, MS
Jarrod Eliason , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO , USA
Marty Depner , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO , USA
John Groat , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO
Daesig Kim , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO , USA
John Walbert , Texas Instruments, 13560 N. Central Expy, MS
Keith Remack , Texas Instruments, 13560 N. Central Expy, MS
Rick Bailey , Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, CO USA
pp. 485
8.1 High Performance Designs

A High Performance Sub-Pipelined Architecture for AES (Abstract)

Hua Li , Department of Mathematics and Computer Science, University of Lethbridge
Jianzhou Li , Department of Mathematics and Computer Science, University of Lethbridge
pp. 491-496

Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications (Abstract)

Hongyu Chen , University of California, San Diego 9500 Gilman Dr., La Jolla, CA
Rui Shi , University of California, San Diego 9500 Gilman Dr., La Jolla, CA
Chung-Kuan Cheng , University of California, San Diego 9500 Gilman Dr., La Jolla, CA
David M. Harris , Harvey Mudd College, Claremont, CA 91711
pp. 497-502

Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm (Abstract)

Tatsuyuki Ishikawa , Graduate School of Information, Production and Systems, Waseda University
Kazunori Shimizu , Graduate School of Information, Production and Systems, Waseda University
Nozomu Togawa , Dept. of Computer Science, Waseda University, Hibikino, Wakamatsuku, Kitakyushu-shi,Japan
Satoshi Goto , Graduate School of Information, Production and Systems, Waseda University
Takeshi Ikenaga , Graduate School of Information, Production and Systems, Waseda University
pp. 503-510

Fast Minimum and Maximum Selection (Abstract)

Anatoly I. Grushin , Moscow Design center, Intel Corporation, Russia
pp. 511-518
8.2 Future VLSI Technologies and Their Impact

Three-Dimensional Cache Design Exploration Using 3DCacti (Abstract)

Yuh-Fang Tsai , Department of Computer Science and Engineering, Penn State University
Yuan Xie , Department of Computer Science and Engineering, Penn State University
Mary Jane Irwin , Department of Computer Science and Engineering, Penn State University
N. Vijaykrishnan , Department of Computer Science and Engineering, Penn State University
pp. 519-524

Implementing Caches in a 3D Technology for High Performance Processors (Abstract)

Gabriel H. Loh , College of Computing
Kiran Puttaswamy , Georgia Institute of Technology School of Electrical and Computer Engineering
pp. 525-532

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors (Abstract)

Wenjing Rao , UC San Diego, CSE Department
Ramesh Karri , Polytechnic University, ECE Department
Alex Orailoglu , UC San Diego, CSE Department
pp. 533-542
8.3 Architecture for Verifiability (Invited)

Formal Verification and its Impact on the Snooping versus Directory Protocol Debate (Abstract)

Milo M. K. Martin , Department of Computer and Information Science University of Pennsylvania
pp. 543-449

Deployment of Better Than Worst-Case Design: Solutions and Needs (Abstract)

Valeria Bertacco , The University of Michigan,Beal Ave, Ann Arbor, MI
Todd Austin , The University of Michigan,Beal Ave, Ann Arbor, MI
pp. 550-558
9.1 Low Power Circuit Architecture (II)

A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS (Abstract)

Maryam Ashouei , Georgia Institute of Technology, Atlanta, GA
Adit D. Singh , Auburn University, Auburn, AL
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Vivek De , Intel Corporation, Hillsboro, OR
pp. 567-573

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction (Abstract)

R.V. Joshi , IBM Austin Research Laboratory, Austin, TX
K.J. Nowka , IBM Austin Research Laboratory, Austin, TX
J.B. Kuang , IBM Austin Research Laboratory, Austin, TX
J.C. Law , IBM Austin Research Laboratory, Austin, TX
H.C. Ngo , IBM Austin Research Laboratory, Austin, TX
pp. 574-584
9.3 Formal Verification Methods

Reconsidering CEGAR: Learning Good Abstractions without Refinement (Abstract)

Edmund Clarke , Carnegie Mellon University, Pittsburgh
Anubhav Gupta , Carnegie Mellon University, Pittsburgh
pp. 591-598

Formal Verification of Parametric Multiplicative Division Implementations (Abstract)

Nikhil Kikkeri , Southern Methodist University, Computer Science and Engineering Dallas, TX
Peter-Michael Seidel , Southern Methodist University, Computer Science and Engineering Dallas, TX
pp. 599-602

Challenges in the Formal Verification of Complete State-of-the-Art Processors (Abstract)

Nikhil Kikkeri , Southern Methodist University, Computer Science and Engineering, Dallas, TX
Nathaniel Ayewah , Southern Methodist University, Computer Science and Engineering, Dallas, TX
Peter-Michael Seidel , Southern Methodist University, Computer Science and Engineering, Dallas, TX
pp. 603-608
10.1 Power and Thermal Consideration in Processor Design (II)

RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free" (Abstract)

Babak Falsafi , Electrical and Computer Engineering, Carnegie Mellon University
Won-Ho Park , Electrical and Computer Engineering, University of Toronto
Andreas Moshovos , Electrical and Computer Engineering, University of Toronto
pp. 609-616

Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism. (Abstract)

Michael Huang , University of Rochester
Luis Pinuel , University Complutense of Madrid
Manuel Prieto , University Complutense of Madrid
Daniel Chaver , University Complutense of Madrid
Fernando Castro , University Complutense of Madrid
Francisco Tirado , University Complutense of Madrid
pp. 617-624

Optimizing the Thermal Behavior of Subarrayed Data Caches (Abstract)

Jie S. Hu , Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ
Johnsy K. John , Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ
Sotirios G. Ziavras , Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ
pp. 625-630

VALVE: Variable Length Value Encoder for Off-Chip Data Buses. (Abstract)

Banit Agrawal , Department of Computer Science and Engineering, University of California, Santa Barbara
Walid A. Najjar , Department of Computer Science and Engineering, University of California, Riverside
Dinesh C. Suresh , Department of Computer Science and Engineering, University of California, Santa Barbara
Jun Yang , Department of Computer Science and Engineering, University of California, Riverside
pp. 631-633

Monitoring Temperature in FPGA based SoCs (Abstract)

John Lach , Departments of Computer Science and Electrical and Computer Engineering University of Virginia.
Mircea Stan , Departments of Computer Science and Electrical and Computer Engineering University of Virginia.
Siva Velusamy , Departments of Computer Science and Electrical and Computer Engineering University of Virginia.
Wei Huang , Departments of Computer Science and Electrical and Computer Engineering University of Virginia.
Kevin Skadron , Departments of Computer Science and Electrical and Computer Engineering University of Virginia.
pp. 634-640
10.2 Instruction Issue, Scheduling and Prediction

Reducing the Energy of Speculative Instruction Schedulers (Abstract)

Glenn Reinman , Department of Electrical and Computer Engineering, Northwestern University
Yongxiang Liu , Computer Science Department, University of California, Los Angeles
Gokhan Memik , Department of Electrical and Computer Engineering, Northwestern University
pp. 641-646

A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation (Abstract)

Mateo Valero , Computer Architecture Department U.P.C. Spain
Alexander V. Veidenbaum , Dep. of Computer Science, University of California Irvine
Luis Villa , Mexican Petroleum Institute
Marco A. Ram?rez , Computer Architecture Department U.P.C. Spain
Adrian Cristal , Computer Architecture Department U.P.C. Spain
pp. 647-653

Power-Efficient Wakeup Tag Broadcast (Abstract)

Dmitry V. Ponomarev , Department of Computer Science, State University of New York at Binghamton
Joseph J. Sharkey , Department of Computer Science, State University of New York at Binghamton
Kanad Ghose , Department of Computer Science, State University of New York at Binghamton
Oguz Ergin , Intel Barcelona Research Center
pp. 654-661

SST: Symbolic Subordinate Threading (Abstract)

Rania Mameesh , Deparmentt of Electrical and Computer Engineering, University of Maryland
Manoh Franklin , Deparmentt of Electrical and Computer Engineering, University of Maryland
pp. 662-665

Memory Bank Predictors (Abstract)

Joan-Manuel Parcerisa , Departament d?Arquitectura de Computadors, Universitat Polit?cnica de Catalunya, Barcelona, Spain
Stefan Bieschewski , Departament d?Arquitectura de Computadors, Universitat Polit?cnica de Catalunya, Barcelona, Spain
Antonio Gonz?lez , Intel Barcelona Research Center, Intel Labs, Universitat Polit?cnica de Catalunya Barcelona, Spain
pp. 666-670
11.1 Circuit Consideration in Process Design

H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication (Abstract)

Sotirios G. Ziavras , Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark, NJ, USA
Xizhen Xu , Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark, NJ, USA
pp. 671-676

Temperature-Sensitive Loop Parallelization for Chip Multiprocessors (Abstract)

Sri Hari Krishna Narayanan , Department of CSE, The Pennsylvania State University
Guilin Chen , Department of CSE, The Pennsylvania State University
Yuan Xie , Department of CSE, The Pennsylvania State University
Mahmut x Mahmut Kandemir, , Department of CSE, The Pennsylvania State University
pp. 677-682

Broadband Impedance Matching for Inductive Interconnect in VLSI Packages (Abstract)

Brock LaMeres , Department of ECE, University of Colorado, Boulder, CO
Sunil P Khatri , Department of EE, Texas A&M University, College Station TX
pp. 683-688

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design (Abstract)

N. Vijaykrishnan , Department of CSE, The Pennsylvania State University, University Park, PA
J. Conner , Department of CSE, The Pennsylvania State University, University Park, PA
G. M. Link , Department of CSE, The Pennsylvania State University, University Park, PA
Yuan Xie , Department of CSE, The Pennsylvania State University, University Park, PA
N. Dhanwad , IBM EDA Laboratory, Hopewell Junction, NY
W.-L. Hung , Department of CSE, The Pennsylvania State University, University Park, PA
pp. 689-696
11.2 Logic Optimization

Temporal Decomposition for Logic Optimization (Abstract)

Nathan Kitchen , University of California at Berkeley, CA, USA
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA, USA
pp. 697-702

Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance (Abstract)

Sam Taylor , School of Computer Science, The University of Manchester
Doug Edwards , School of Computer Science, The University of Manchester
Luis A. Plana , School of Computer Science, The University of Manchester
pp. 703-710

An Improved Approach for AlternativeWires Identi.cation (Abstract)

Chun-Yao Wang , Department of Computer Science, National Tsing Hua University, HsingChu, Taiwan
Yung-Chih Chen , Department of Computer Science, National Tsing Hua University, HsingChu, Taiwan
pp. 711-716
Author Index

Author Index (PDF)

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