The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (2005)
San Jose, California
Oct. 2, 2005 to Oct. 5, 2005
ISBN: 0-7695-2451-6
pp: 479-484
Thomas Rinderknecht , Mentor Graphics Corp. Wilsonville, OR
Wu-Tung Cheng , Mentor Graphics Corp. Wilsonville, OR
Janak H. Patel , University of Illinois at Urbana-Champaign, Urbana, IL
Liyang Lai , University of Illinois at Urbana-Champaign, Urbana, IL
ABSTRACT
<p>In this paper, a novel logic BIST (built-in self test) scheme with complementary weights is proposed. The BIST implementation combines random patterns with complementary-weight weighted patterns. A heuristic algorithm based on deterministic test set is developed to compute weight set with complementary weights. Hardware similar to bit-flipping is used to produce complementary weights. For random resistant ISCAS circuits, complete fault coverage can be achieved with very low hardware overhead. Experiments show that two complementary weights are sufficient for weighted random pattern testing and it presents a novel direction for exploiting weighted patterns.</p>
INDEX TERMS
null
CITATION
Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel, Liyang Lai, "Hardware Ef.cient LBISTWith Complementary Weights", 2012 IEEE 30th International Conference on Computer Design (ICCD), vol. 00, no. , pp. 479-484, 2005, doi:10.1109/ICCD.2005.63
92 ms
(Ver 3.3 (11022016))