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2005 International Conference on Computer Design (2005)
San Jose, California
Oct. 2, 2005 to Oct. 5, 2005
ISBN: 0-7695-2451-6
pp: 206-214
N. Banerjee , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
A. Raychowdhury , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
S. Bhunia , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
H. Mahmoodi , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
K. Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
ABSTRACT
<p>Abstract: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce redundant switching in datapaths. However, they incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce the overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and application of operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a complete flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques can achieve at least 40% reduction in power consumption compared to the original circuit with minimal area overhead (5%) and small delay penalty (0.15%).</p>
INDEX TERMS
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CITATION

A. Raychowdhury, N. Banerjee, S. Bhunia, H. Mahmoodi and K. Roy, "Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis," 2005 International Conference on Computer Design(ICCD), San Jose, California, 2005, pp. 206-214.
doi:10.1109/ICCD.2005.80
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