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2012 IEEE 30th International Conference on Computer Design (ICCD) (2004)
San Jose, CA
Oct. 11, 2004 to Oct. 13, 2004
ISSN: 1063-6404
ISBN: 0-7695-2231-9
TABLE OF CONTENTS

Welcome Letter (PDF)

pp. xii-xiii

Program Committee (PDF)

pp. xv-xvi

Additional Reviewers (PDF)

pp. xvii-xviii
Keynote Addresses
Session 1.1 High-Speed and Energy-Efficient Circuit Design

PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks (Abstract)

Mehrdad Nourani , The University of Texas at Dallas
Deepak S. Vijayasarathi , The University of Texas at Dallas
Poras T. Balsara , The University of Texas at Dallas
Mohammad J. Akhbarizadeh , The University of Texas at Dallas
pp. 6-11

Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses (Abstract)

Srinivasa R. Sridhara , University of Illinois at Urbana Champaign
Naresh R. Shanbhag , University of Illinois at Urbana Champaign
Arshad Ahmed , University of Illinois at Urbana Champaign
pp. 12-17

An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices (Abstract)

Montek Singh , University of North Carolina, Chapel Hill
Anselmo Lastra , University of North Carolina, Chapel Hill
Justin Hensley , University of North Carolina, Chapel Hill
pp. 18-25

A High-Frequency Decimal Multiplier (Abstract)

Robert D. Kenney , University of Wisconsin - Madison
Mark A. Erle , International Business Machines, Poughkeepsie, NY
Michael J. Schulte , University of Wisconsin - Madison
pp. 26-29

An Efficient Twin-Precision Multiplier (Abstract)

Per Larsson-Edefors , Chalmers University of Technology, Sweden
Magnus Sj?lander , Chalmers University of Technology, Sweden
Henrik Eriksson , Chalmers University of Technology, Sweden
pp. 30-33
Session 1.2 Energy-Efficient Processor Microarchitecture (1)

Defining Wakeup Width for Efficient Dynamic Scheduling (Abstract)

Manoj Franklin , University of Maryland, College Park
Oguz Ergin , Binghamton University, NY
Aneesh Aggarwal , Binghamton University, NY
pp. 36-41

Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure (Abstract)

Gi-Ho Park , Samsung Electronics Co., LTD. Giheung, Korea
Jung-Wook Park , CS, Yonsei University, Korea
Sung-Bae Park , Samsung Electronics Co., LTD. Giheung, Korea
Shin-Dug Kim , CS, Yonsei University, Korea
pp. 42-47

Thermal-Aware Clustered Microarchitectures (Abstract)

Jos? Gonz?lez , Intel Barcelona Research Center - Intel Labs - UPC
Antonio Gonz?lez , Intel Barcelona Research Center - Intel Labs - UPC
Pedro Chaparro , Intel Barcelona Research Center - Intel Labs - UPC
pp. 48-53

Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm (Abstract)

Yu Bai , Brown University, Providence, RI
R. Iris Bahar , Brown University, Providence, RI
pp. 54-57
Session 1.3 Scan Design and Test

A Novel Low-Power Scan Design Technique Using Supply Gating (Abstract)

S. Bhunia , Purdue University, West Lafayette, IN
S. Mukhopadhyay , Purdue University, West Lafayette, IN
D. Ghosh , Purdue University, West Lafayette, IN
H. Mahmoodi , Purdue University, West Lafayette, IN
K. Roy , Purdue University, West Lafayette, IN
pp. 60-65

Asynchronous Scan-Latch controller for Low Area Overhead DFT (Abstract)

Takashi Nanya , The University of Tokyo, Japan
Masayuki Tsukisaka , The University of Tokyo, Japan
Masashi Imai , The University of Tokyo, Japan
pp. 66-71

End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths (Abstract)

Alex Orailoglu , UCSD, San Diego, CA
Sule Ozev , Duke University, Durham, NC
pp. 72-77

Functional Illinois Scan Design at RTL (Abstract)

Nicola Nicolici , McMaster University, Hamilton, ON, Canada
Ho Fai Ko , McMaster University, Hamilton, ON, Canada
pp. 78-81

On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 82-84
Session 2.1 Routing and Floorplanning

A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits (Abstract)

Hasan Arslan , University of Illinois-Chicago
Shantanu Dutt , University of Illinois-Chicago
pp. 86-92

A Two-Layer Bus Routing Algorithm for High-Speed Boards (Abstract)

Muhammet Mustafa Ozdal , Univ. of Illinois at Urbana-Champaign
Martin D. F. Wong , Univ. of Illinois at Urbana-Champaign
pp. 99-105

Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers (Abstract)

Sherief Reda , University of CA, San Diego
Andrew B. Kahng , University of CA, San Diego
pp. 106-110
Session 2.2 Formal Verification Embedded Tutorial

Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking (Abstract)

Chao Wang , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
Gary D. Hachtel , University of Colorado at Boulder
pp. 112-118
Session 2.3 Signal Integrity and Leakage

A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits (Abstract)

Srivathsan Krishnamohan , Michigan State University, East Lansing, MI
Nihar R. Mahapatra , Michigan State University, East Lansing, MI
pp. 126-131

A Signal Integrity Test Bed for PCB Buses (Abstract)

Jihong Ren , University of British Columbia
Mark R. Greenstreet , University of British Columbia
pp. 132-137

A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters (Abstract)

Dennis Sylvester , University of Michigan, Ann Arbor
Saumil Shah , University of Michigan, Ann Arbor
Kanak Agarwal , University of Michigan, Ann Arbor
pp. 138-143

A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs (Abstract)

Kevin Skadron , University of Virginia
John Lach , University of Virginia
Jason Brandon , University of Virginia
pp. 144-150
Session 3.1 Special Session on High-Performance On-Chip Communication

Design Methodologies and Architecture Solutions for High-Performance Interconnects (Abstract)

Livio Baldi , STMicroelectronics, Italy
Davide Pandini , STMicroelectronics, Italy
Cristiano Forzan , STMicroelectronics, Italy
pp. 152-159

On-Chip Transparent Wire Pipelining (Abstract)

Mario R. Casu , Politecnico di Torino, Italy
Luca Macchiarulo , Politecnico di Torino, Italy
pp. 160-167

Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Larry Pileggi , Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 168-173

Network-on-Chip: The Intelligence is in The Wire (Abstract)

Philippe Martin , Arteris, France
Gerard Mas , STMicroelectronics, France
pp. 174-177
Session 3.2 Test Generation and Characterization

Low Power Test Data Compression Based on LFSR Reseeding (Abstract)

Jinkyu Lee , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 180-185

An Infrastructure IP for On-Chip Clock Jitter Measurement (Abstract)

Jiun-Lang Huang , National Taiwan University, Taipei
Jui-Jer Huang , Industrial Technology Research Institute, Taiwan
pp. 186-191

Diagnosis of Hold Time Defects (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
Zhiyuan Wang , University of California, Santa Barbara
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 192-199

Extending the Applicability of Parallel-Serial Scan Designs (Abstract)

Baris Arslan , University of California, San Diego
Alex Orailoglu , University of California, San Diego
Ozgur Sinanoglu , University of California, San Diego
pp. 200-203

Quality Improvement Methods for System-Level Stimuli Generation (Abstract)

Yehuda Naveh , Haifa University Campus, Israel
Itai Jaeger , Haifa University Campus, Israel
Roy Emek , Haifa University Campus, Israel
Yoav Katz , Haifa University Campus, Israel
pp. 204-206
Session 3.3 Physically-Aware Design Tools

XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs (Abstract)

Takashi Miyoshi , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Ashwini Verma , Amdocs, San Jose, CA
Yinghua Li , UC Berkeley, Berkeley, CA
pp. 208-215

A Flexible Data Structure for Efficient Buffer Insertion (Abstract)

Ruiming Chen , Northwestern University, Evanston, IL
Hai Zhou , Northwestern University, Evanston, IL
pp. 216-221

Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis, MN
Anup Kumar Sultania , University of Minnesota, Minneapolis, MN
Dennis Sylvester , University of Michigan, Ann Arbor, MI
pp. 228-233
Session 4.1 Energy-Efficient Processor Microarchitecture (2)

Best of Both Latency and Throughput (Abstract)

Ed Grochowski , Intel Labs, Santa Clara, CA
Ronny Ronen , Intel Israel
John Shen , Intel Labs, Santa Clara, CA
Hong Wang , Intel Labs, Santa Clara, CA
pp. 236-243

Fetch Halting on Critical Load Misses (Abstract)

Brian Singer , Brown University, Providence, RI
Michael Leuchtenburg , Hampshire College, Amherst, MA
R. Iris Bahar , Brown University, Providence, RI
Richard Weiss , Hampshire College, Amherst, MA
Nikil Mehta , Brown University, Providence, RI
pp. 244-249

Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2 (Abstract)

Jos? Gonz?lez , Intel Barcelona Research Center
Grigorios Magklis , Intel Barcelona Research Center
Antonio Gonz?lez , Intel Barcelona Research Center
pp. 250-255
Session 4.2 Power and Timing Optimization

Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction (Abstract)

John P. Hayes , University of Michigan, Ann Arbor
Feng Gao , University of Michigan, Ann Arbor
pp. 258-264

Potential Slack Budgeting with Clock Skew Optimization (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Kai Wang , University of California, Santa Barbara
pp. 265-271

A New Statistical Optimization Algorithm for Gate Sizing (Abstract)

Murari Mani , University of Texas at Austin
Michael Orshansky , University of Texas at Austin
pp. 272-277
Session 4.3 Novel Processor Design

An Architecture for Fast Processing of Large Unstructured Data Sets (Abstract)

Jason White , Data Search Systems, Inc., St. Louis, MO
Berkley Shands , Washington University in St. Louis
Roger Chamberlain , Washington University in St. Louis; Data Search Systems, Inc., St. Louis, MO
Mark Franklin , Washington University in St. Louis
Michael Henrichs , Data Search Systems, Inc., St. Louis, MO
pp. 280-287

In-System FPGA Prototyping of an Itanium Microarchitecture (Abstract)

James C. Hoe , Computer Architecture Laboratory at Carnegie Mellon
Roland E. Wunderlich , Computer Architecture Laboratory at Carnegie Mellon
pp. 288-294

Adaptive Selection of an Index in a Texture Cache (Abstract)

Chun-Ho Kim , KAIST (Korea Advanced Institute of Science and Technology)
Lee-Sup Kim , KAIST (Korea Advanced Institute of Science and Technology)
pp. 295-300
Session 5.1 Emerging Technologies Special Session

Using Circuits and Systems-Level Research to Drive Nanotechnology (Abstract)

Ramprasad Ravichandran , Georgia Institute of Technology
Peter M. Kogge , University of Notre Dame
Michael T. Niemier , Georgia Institute of Technology
pp. 302-309

FPGA Emulation of Quantum Circuits (Abstract)

Zeljko Zilic , McGill University, Montreal, Quebec
Ahmed Usman Khalid , McGill University, Montreal, Quebec
Katarzyna Radecka , Concordia University, Montreal, Quebec
pp. 310-315

3D Processing Technology and Its Impact on iA32 Microprocessors (Abstract)

Clair Webb , Intel Corporation
Donald W. Nelson , Intel Corporation
Bryan Black , Intel Corporation
Nick Samra , Intel Corporation
pp. 316-318
Session 5.2 Cache Memory Design

Cache Array Architecture Optimization at Deep Submicron Technologies (Abstract)

Ronald J. Gutmann , Rensselaer Polytechnic Institute, Troy, NY
Ken Rose , Rensselaer Polytechnic Institute, Troy, NY
Annie Y. Zeng , Rensselaer Polytechnic Institute, Troy, NY
pp. 320-325

Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling (Abstract)

Joshua L. Kihm , University of Colorado at Boulder
Daniel A. Connors , University of Colorado at Boulder
pp. 326-331

Low Energy, Highly-Associative Cache Design for Embedded Processors (Abstract)

Alex Veidenbaum , University of California, Irvine
Dan Nicolaescu , University of California, Irvine
pp. 332-335
Session 6.1 Layout-Driven Circuit Optimization

The Magic of a Via-Configurable Regular Fabric (Abstract)

Yajun Ran , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 338-343

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network (Abstract)

Qiang Zhou , Tsinghua University, Beijing, P.R. China
Xianlong Hong , Tsinghua University, Beijing, P.R. China
Sheldon X.-D. Tan , University of California at Riverside, USA
Yi Zou , Tsinghua University, Beijing, P.R. China
Yici Cai , Tsinghua University, Beijing, P.R. China
pp. 344-349

Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning (Abstract)

Michel Berkelaar , Magma Design Automation Inc., Cupertino, CA, USA
Wolfgang Kunz , University of Kaiserslautern, Germany
Ingmar Neumann , University of Kaiserslautern, Germany
Kolja Sulimma , University of Kaiserslautern, Germany
Dominik Stoffel , University of Kaiserslautern, Germany
pp. 350-353

Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed (Abstract)

Hunsoo Choo , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Dongku Kang , Purdue University, West Lafayette, IN
pp. 354-357
Session 6.2 Instruction-Level Parallelism (1)

A Minimal Dual-Core Speculative Multi-Threading Architecture (Abstract)

Konrad Lai , Intel Corporation
Tom Holman , Intel Corporation
Haitham Akkary , Intel Corporation
Srikanth T. Srinivasan , Intel Corporation
pp. 360-367

Exploiting Quiescent States in Register Lifetime (Abstract)

Arun K. Somani , Iowa State University, Ames
Rama Sangireddy , University of Texas at Dallas
pp. 368-374

Evaluating Techniques for Exploiting Instruction Slack (Abstract)

John Sheu , Harvard University
David Brooks , Harvard University
Yau Chin , Harvard University
pp. 375-378
Session 6.3 Power Estimation and Minimization

Static Transition Probability Analysis Under Uncertainty (Abstract)

Siddharth Tata , Indian Institute of Technology-Madras
Siddharth Garg , Indian Institute of Technology-Madras
Ravishankar Arunachalam , Indian Institute of Technology-Madras
pp. 380-386

Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation (Abstract)

Donald Chai , University of California at Berkeley, CA, USA
Andreas Kuehlmann , University of California at Berkeley, CA, USA; Cadence Berkeley Labs, Berkeley, CA, USA
pp. 387-392

Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor (Abstract)

Massimo Poncino , Universit? di Verona, Italy
Luca Benini , Universit? di Bologna, Italy
Mirko Loghi , Universit? di Verona, Italy
pp. 393-396

An Architectural Power Estimator for Analog-to-Digital Converters (Abstract)

Zhaohui Huang , Michigan State University, East Lansing, MI
Peixin Zhong , Michigan State University, East Lansing, MI
pp. 397-400
Session 7.1 Formal Verification Techniques

Formal Hardware Verification based on Signal Correlation Properties (Abstract)

Nikhil Kikkeri , Southern Methodist University, Dallas, TX
Peter-Michael Seidel , Southern Methodist University, Dallas, TX
pp. 402-408

Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs (Abstract)

Alan J. Hu , University of British Columbia
Jin Yang , Intel Corporation
Kelvin Ng , University of British Columbia
pp. 409-416

Graph Automorphism-Based Algorithm for Determining Symmetric Inputs (Abstract)

Chun-Yao Wang , National Tsing Hua University, Taiwan
Jing-Yang Jou , National Chiao Tung University, Taiwan
Chen-Ling Chou , National Chiao Tung University, Taiwan
Geeng-Wei Lee , National Chiao Tung University, Taiwan
pp. 417-419
Session 7.2 Networks on Chips

Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures (Abstract)

Karam S. Chatha , Arizona State University, Tempe
Goran Konjevod , Arizona State University, Tempe
Krishnan Srinivasan , Arizona State University, Tempe
pp. 422-429

Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture (Abstract)

W. Hung , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
T. Theocharides , The Pennsylvania State University
Y. Xie , The Pennsylvania State University
C. Addo-Quaye , The Pennsylvania State University
M. J. Irwin , The Pennsylvania State University
pp. 430-437

Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures (Abstract)

Han-You Jeong , Seoul National University, Korea
Chae-Eun Rhee , Samsung Electronics Co., Ltd, Suwon, Korea
Soonhoi Ha , Seoul National University, Korea
pp. 438-443
Session 7.3 Novel Processor Architecture

An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing (Abstract)

Chaoxian Zhou , Chinese Academy of Science
Jie Chen , Chinese Academy of Science
Baofeng Li , Chinese Academy of Science
Xiaoyun Wei , Chinese Academy of Science
Ying Li , Chinese Academy of Science
Xin Zhang , Chinese Academy of Science
Zhibi Liu , Chinese Academy of Science
Liang Han , Chinese Academy of Science
pp. 446-451

Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study (Abstract)

Jiangjiang Liu , University at Buffalo, SUNY, NY
Krishnan Sundaresan , Michigan State University, East Lansing
Nihar R. Mahapatra , Michigan State University, East Lansing
pp. 458-463
Session 8.1 Instruction-Level Parallelism (2)

Compiler-Based Frame Formation for Static Optimization (Abstract)

Yiorgos Makris , Yale University, New Haven, CT
Sobeeh Almukhaizim , Yale University, New Haven, CT
Feng Shi , Yale University, New Haven, CT
Pey-Chang Lin , Yale University, New Haven, CT
pp. 466-471

IPC Driven Dynamic Associative Cache Architecture for Low Energy (Abstract)

Akhilesh Tyagi , Iowa State University, Ames, Iowa
Sriram Nadathur , Iowa State University, Ames, Iowa
pp. 472-479

Increasing Processor Performance Through Early Register Release (Abstract)

Deniz Balkan , State University of New York, Binghamton, NY
Oguz Ergin , State University of New York, Binghamton, NY
Kanad Ghose , State University of New York, Binghamton, NY
Dmitry Ponomarev , State University of New York, Binghamton, NY
pp. 480-487
Session 8.2 Topics in Synthesis and Co-Simulation

Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field Programmable Analog Arrays (Abstract)

Hu Huang , University of Maryland, College Park, MD
Joseph B. Bernstein , University of Maryland, College Park, MD
Martin Peckerar , University of Maryland, College Park, MD
Ji Luo , University of Maryland, College Park, MD
pp. 490-495

Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures (Abstract)

M. Monguzzi , Sitek S.p.A., S.G. Lupatoto, Italy
F. Fummi , Universit? di Verona, Italy
S. Martini , Embedded Systems Design Center, Verona, Italy
M. Poncino , Universit? di Verona, Italy
G. Perbellini , Embedded Systems Design Center, Verona, Italy
pp. 496-501

Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC (Abstract)

Jinwen Xi , Michigan State University, East Lansing, MI
Peixin Zhong , Michigan State University, East Lansing, MI
pp. 502-504

Coping with The Variability of Combinational Logic Delays (Abstract)

L. Lavagno , Politenico di Torino, Italy
J. Cortadella , Univ. Polit?cnica Catalunya, Barcelona, Spain
C. Sotiriou , ICS-FORTH, Crete, Greece
A. Kondratyev , Cadence Berkeley Labs, Berkeley, CA
pp. 505-508
Session 8.3 Low-Power Architecture

Design-Space Exploration of Power-Aware On/Off Interconnection Networks (Abstract)

Vassos Soteriou , Princeton University, Princeton, NJ
Li-Shiuan Peh , Princeton University, Princeton, NJ
pp. 510-517

Energy Characterization of Hardware-Based Data Prefetching (Abstract)

Saurabh Chheda , BlueRISC Inc., Hadley, MA
Yao Guo , University of Massachusetts, Amherst, MA
C. Mani Krishna , University of Massachusetts, Amherst, MA
Israel Koren , University of Massachusetts, Amherst, MA
Csaba Andras Moritz , University of Massachusetts, Amherst, MA
pp. 518-523

Design and Implementation of Scalable Low-Power Montgomery Multiplier (Abstract)

Hee-Kwan Son , Samsung Electronics Co., Korea
Sang-Geun Oh , Samsung Electronics Co., Korea
pp. 524-531
Session 9.1 Test Generation

Compressed Embedded Diagnosis of Logic Cores (Abstract)

Adam B. Kinsman , McMaster University, ON, Canada
Scott Ollivierre , McMaster University, ON, Canada
Nicola Nicolici , McMaster University, ON, Canada
pp. 534-539

An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks (Abstract)

Niraj K. Jha , Princeton University, NJ
Pallav Gupta , Princeton University, NJ
Rui Zhang , Princeton University, NJ
pp. 540-543

An Efficient Algorithm for Reconfiguring Shared Spare RRAM (Abstract)

Fu-Min Yeh , Chung-Shan Institute of Science and Technology, Taoyuan, Taiwan
Hung-Yau Lin , National Taiwan University, Taipei
Sy-Yen Kuo , National Taiwan University, Taipei
Ing-Yi Chen , National Taipei University of Technology, Taiwan
Hong-Zu v , National Taiwan University, Taipei
pp. 544-546
Session 9.2 Network Routing

An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems (Abstract)

H. Sarbazi-azad , IPM, Tehran, Iran; Sharif Univ. of Technology, Tehran, Iran
H. H. Najaf-abadi , IPM, Tehran, Iran
pp. 548-553

Technique to Eliminate Sorting in IP Packet Forwarding Devices (Abstract)

Raymond W. Baldwin , University of Illinois at Chicago
Enrico Ng , University of Illinois at Chicago
pp. 554-559
Session 9.3 Placement and Floorplanning

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design (Abstract)

Muzhou Shao , Synopsys Inc., Mountain View, CA
Hung-Ming Chen , National Chiao Tung University, Hsinchu, Taiwan
I-Min Liu , Cadence Design Systems Inc., San Jose, CA
Li-Da Huang , Texas Instruments, Austin, TX
Martin D.F. Wong , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 562-567

Placement with Alignment and Performance Constraints Using the B*-Tree Representation (Abstract)

Yao-Wen Chang , National Taiwan University, Taipei
Meng-Chen Wu , National Chiao Tung University, Taiwan
pp. 568-571

ACG-Adjacent Constraint Graph for General Floorplans (Abstract)

Jia Wang , Northwestern University, Evanston, IL
Hai Zhou , Northwestern University, Evanston, IL
pp. 572-575

Author Index (PDF)

pp. 576-578
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