The Community for Technology Leaders
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. (2004)
San Jose, CA
Oct. 11, 2004 to Oct. 13, 2004
ISSN: 1063-6404
ISBN: 0-7695-2231-9
pp: 222-227
Madhubanti Mukherjee , University of Cincinnati, OH
Ranga Vemuri , University of Cincinnati, OH
ABSTRACT
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical synthesis issues for such systems. Such efforts showed a significant reduction in interconnect lengths. In order to effectively synthesize designs for 3D systems, it is necessary to take layer assignment for resources into consideration at higher levels of the design abstraction. We address the layer assignment problem as a part of a physical aware behavioral synthesis flow. We propose a 0-1 linear program formulation to perform simultaneous and optimal scheduling, binding and layer assignment for synthesizing designs for three-dimensional vertically integrated systems. The objective is to minimize inter-stratal via and the interconnect length in the critical path while taking thermal gradient between layers into account (which has been shown to be of particular concern for 3D systems). Floorplanning is performed for the synthesized design in order to estimate interconnect lengths. Results show a reduction of approximately 37% in total interconnect lengths on an average, compared to a traditional two-dimensional implementation when 2-5 layer implementations are examined.
INDEX TERMS
null
CITATION

M. Mukherjee and R. Vemuri, "Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems," IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.(ICCD), San Jose, CA, 2004, pp. 222-227.
doi:10.1109/ICCD.2004.1347926
90 ms
(Ver 3.3 (11022016))