The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (2003)
San Jose, California
Oct. 13, 2003 to Oct. 15, 2003
ISSN: 1063-6404
ISBN: 0-7695-2025-1
TABLE OF CONTENTS

Welcome (PDF)

pp. xiii
Keynotes

High-Speed Link Design, Then and Now (PDF)

Mark Horowitz , Stanford University
pp. xx

Advanced EDA Tools for High-Performance Design (PDF)

Ted Vucurevich , Cadence Design Systems, Inc.
pp. xxii
Session 1.1 Energy Efficiency

Energy Efficient Asymmetrically Ported Register Files (Abstract)

Manoj Franklin , University of Maryland
Aneesh Aggarwal , University of Maryland
pp. 2

Power Efficient Data Cache Designs (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya, Barcelona (Spain)
Jaume Abella , Universitat Polit?cnica de Catalunya, Barcelona (Spain)
pp. 8

On Reducing Register Pressure and Energy in Multiple-Banked Register Files (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya, Barcelona (Spain)
Jaume Abella , Universitat Polit?cnica de Catalunya, Barcelona (Spain)
pp. 14
Session 1.2 Timing Verification

Verification of Timed Circuits with Failure Directed Abstractions (Abstract)

Hao Zheng , IBM Microelectronics in Burlington, VT
Scott Little , University of Utah, Salt Lake City
David Walter , University of Utah, Salt Lake City
Tomohiro Yoneda , National Institute of Informatics in Tokyo, Japan.
Chris J. Myers , University of Utah, Salt Lake City
pp. 28

Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits (Abstract)

Marong Phadoongsidhi , University of Wisconsin - Madison
Kewal K. Saluja , University of Wisconsin - Madison
pp. 42

Specifying and Verifying Systems with Multiple Clocks (Abstract)

Edmund M. Clarke , Carnegie Mellon University
Karen Yorav , Carnegie Mellon University
Daniel Kroening , Carnegie Mellon University
pp. 48
Session 1.3 Electrical Analysis for System LSI

An Improved method for Fast Noise Estimation based on Net Segmentation (Abstract)

Aurobindo Dasgupta , Intel Corporation, Austin, Texas
Chih-Liang Huang , Intel Corporation, Austin, Texas
pp. 64

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current (Abstract)

R. Iris Bahar , Brown University
S. Bohidar , Brown University
Joel Grodstein , Intel Massachusetts
H.-Y. Song , Brown University
pp. 70

An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis, MN
Venkatesan Rajappan , Synplicity Inc., Sunnyvale, CA
pp. 76
Session 2.1 Power Optimization

A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors (Abstract)

Rick Stephani , Advance Custom Memory Group, AMINN
Dechang Sun , Advance Custom Memory Group, AMINN
Payman Zarkesh-Ha , LSI Logic Corporation
Gordon Priebe , Advance Custom Memory Group, AMINN
William Loh , LSI Logic Corporation
Ken Doniger , LSI Logic Corporation
pp. 84

Precomputation-based Guarding for Dynamic and Leakage Power Reduction (Abstract)

Afshin Abdollahi , University of Southern California
Massoud Pedarm , University of Southern California
Indradeep Ghosh , Fujitsu Labs of America
Farzan Fallah , Fujitsu Labs of America
pp. 90

Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits (Abstract)

Zheng Xu , Columbia University, New York
Saravanan Rajapandian , Columbia University, New York
K. L. Shepard , Columbia University, New York
pp. 98

Low Power Adder with Adaptive Supply Voltage (Abstract)

Hiroaki Suzuki , Purdue University, West Lafayette
Woopyo Jeong , Purdue University, West Lafayette
Kaushik Roy , Purdue University, West Lafayette
pp. 103
Session 2.2 Invited Session: Gene Chip Design
Embedded Tutorial

Design Flow Enhancements for DNA Arrays (Abstract)

Xu Xu , University of California at San Diego
Sherief Reda , University of California at San Diego
Andrew B. Kahng , University of California at San Diego
Alex Z. Zelikovsky , Georgia State University
Ion I. Mandoiu , University of Connecticut
pp. 116
Session 2.3 System Level Design

Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip (Abstract)

Nattawut Thepayasuwan , State University of New York at Stony Brook
Alex Doboli , State University of New York at Stony Brook
Vaishali Damle , State University of New York at Stony Brook
pp. 126

Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs (Abstract)

Vikas Chandra , Carnegie Mellon University, Pittsburgh, PA
Jeff Burns , IBM Austin Research Lab
Gary Carpenter , IBM Austin Research Lab
pp. 134

Interface Synthesis using Memory Mapping for an FPGA Platform (Abstract)

Alex Nicolau , University of California at Irvine
Rajesh Gupta , University of California at San Diego
Manev Luthra , University of California at Irvine
Sumit Gupta , University of California at Irvine
Nikil Dutt , University of California at Irvine
pp. 140

Efficient Synthesis of Networks On Chip (Abstract)

Alessandro Pinto , University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
Luca P. Carloni , University of California at Berkeley
pp. 146

Reducing Compilation Time Overhead in Compiled Simulators (Abstract)

Mehrdad Reshadi , University of California, Irvine
Nikil Dutt , University of California, Irvine
pp. 151
Session 3.1 Systems Performance

Profiling Interrupt Handler Performance through Kernel Instrumentation (Abstract)

Thomas Slabach , University of Notre Dame
Lambert Schaelicke , University of Notre Dame
Branden Moore , University of Notre Dame
pp. 156

Routed Inter-ALU Networks for ILP Scalability and Performance (Abstract)

Stephen W. Keckler , The University of Texas at Austin
Karthikeyan Sankaralingam , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Vincent Ajay Singh , The University of Texas at Austin
pp. 170
Session 3.2 Micro Processor Test & Diagnosis

Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor (Abstract)

Vijay Bettada , Intel Corporation, Shrewsbury, MA
Joel Grodstein , Intel Corporation, Shrewsbury, MA
Richard Davies , Intel Corporation, Shrewsbury, MA
Dilip Bhavsar , Intel Corporation, Shrewsbury, MA
pp. 180

Multiple Fault Diagnosis Using n-Detection Tests (Abstract)

Zhiyuan Wang , University of California, Santa Barbara
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 198
Session 3.3 Physical Design

A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor (Abstract)

Yoshiyasu Tanamura , Fujitsu Limited, Japan
Ryoichi Yamashita , Fujitsu Limited, Japan
Hiroaki Komatsu , Fujitsu Limited, Japan
Hirofumi Hamamura , Fujitsu Limited, Japan
Yaroku Sugiyama , Fujitsu Limited, Japan
Noriyuki Ito , Fujitsu Limited, Japan
Hiroyuki Sugiyama , Fujitsu Limited, Japan
pp. 204

Physical Design of the "2.5D" Stacked System (Abstract)

Yangdong (Steven) Deng , Carnegie Mellon University, Pittsburgh, PA
Wojciech Maly , Carnegie Mellon University, Pittsburgh, PA
pp. 211

Flow-Based Cell Moving Algorithm for Desired Cell Distribution (Abstract)

Bo-Kyung Choi , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
Huaiyu Xu , University of California, Los Angeles
Maogang Wang , Cadence Design Systems, San Jose, CA
pp. 218
Session 4.1 Performance Optimization

NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors (Abstract)

Lizy Kurian John , The University of Texas at Austin
Byeong Kil Lee , The University of Texas at Austin
pp. 226

Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis (Abstract)

Krishnan Sundaresan , Michigan State University
Nihar R. Mahapatra , Michigan State University
Jiangjiang Liu , University at Buffalo, SUNY
pp. 234

Pipelined Multiplicative Division with IEEE Rounding (Abstract)

Guy Even , Tel-Aviv University
Peter-M. Seidel , Southern Methodist University
pp. 240
Session 4.2 Clock & Signal Distribution

Design of Resonant Global Clock Distributions (Abstract)

Kenneth L. Shepard , Columbia University, New York, NY
Steven C. Chan , Columbia University, New York, NY
Phillip J. Restle , IBM T.J Watson Research Center, NY
pp. 248

Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links (Abstract)

Ganesh Balamurugan , University of Illinois at Urbana-Champaign, Urbana, IL
Naresh Shanbhag , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 254

A Mixed-Mode Delay-Locked-Loop Architecture (Abstract)

Daniel Eckerbert , Chalmers University of Technology, Sweden
Lars "J." Svensson , Chalmers University of Technology, Sweden
Per Larsson-Edefors , Chalmers University of Technology, Sweden
pp. 261

Optimal Inductance for On-chip RLC Interconnections (Abstract)

David Blaauw , University of Michigan, Ann Arbor
Kanak Agarwal , University of Michigan, Ann Arbor
Shidhartha Das , University of Michigan, Ann Arbor
Dennis Sylvester , University of Michigan, Ann Arbor
pp. 264
Session 4.3 Performance and Power-Driven Physical Design

Spec Based Flip-Flop And Buffer Insertion (Abstract)

Nataraj Akkiraju , Intel Corporation, Santa Clara, CA
Mosur Mohan , Intel Corporation, Hilsboro, OR
pp. 270

A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization (Abstract)

Ashok K. Murugavel , University of South Florida, Tampa
N. Ranganathan , University of South Florida, Tampa
pp. 276

A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing (Abstract)

Rishi Chaturvedi , Texas A&M University, College Station
Jiang Hu , Texas A&M University, College Station
pp. 282
Session 5.1 Instruction Execution

Hardware-based Pointer Data Prefetcher (Abstract)

Shih-Lien Lu , Intel corp., Hillsboro, OR
Shih-Chang Lai , SiS Corporation, Hsinchu, Taiwan
pp. 290

A Dependence Driven Efficient Dispatch Scheme (Abstract)

Sriram Nadathur , Iowa State University, Ames
Akhilesh Tyagi , Iowa State University, Ames
pp. 299

An Efficient VLIW DSP Architecture for Baseband Processing (Abstract)

Chein-Wei Jen , National Chiao Tung University
Chin-Chi Chang , National Chiao Tung University
Chen-Chia Lee , National Chiao Tung University
Tay-Jyi Lin , National Chiao Tung University
pp. 307

Dynamic Thread Resizing for Speculative Multithreaded Processors (Abstract)

Manoj Franklin , University of Maryland, College Park
Mohamed Zahran , University of Maryland, College Park
pp. 313
Session 5.2 Invited Session: Test Compression Technology

XMAX: X-Tolerant Architecture for MAXimal Test Compression (Abstract)

Subhasish Mitra , Intel Corporation, Sacramento, CA
Kee Sup Kim , Intel Corporation, Sacramento, CA
pp. 326

Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs (Abstract)

Jerzy Tyszer , Poznan University of Technology
Janusz Rajski , Mentor Graphics Corporation
pp. 331
Session 5.3 Physical Design for Regular Fabrics and FPGA's

Non-Crossing OBDDs for Mapping to Regular Circuit Structures (Abstract)

Cheng-Kok Koh , School of Electrical and Purdue University
Aiqun Cao , School of Electrical and Purdue University
pp. 338

Interconnect Estimation for FPGAs under Timing Driven Domains (Abstract)

Parivallal Kannan , University of Texas at Dallas
Dinesh Bhatia , University of Texas at Dallas
pp. 344

ROAD : An Order-Impervious Optimal Detailed Router for FPGAs (Abstract)

Hasan Arslan , University of Illinois-Chicago
Shantanu Dutt , University of Illinois-Chicago
pp. 350
Session 6.1 Array Design Optimization

Reducing dTLB Energy Through Dynamic Resizing (Abstract)

M. J. Irwin , The Pennsylvania State University
V. Delaluz , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
A. Sivasubramaniam , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
pp. 358

Distributed Reorder Buffer Schemes for Low Power (Abstract)

Oguz Ergin , State University of New York, Binghamton
Gurhan Kucuk , State University of New York, Binghamton
Kanad Ghose , State University of New York, Binghamton
Dmitry Ponomarev , State University of New York, Binghamton
pp. 364

Virtual Page Tag Reduction for Low-power TLBs (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 371

Dynamic Cluster Resizing (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya
Jos? Gonz?lez , Universitat Polit?cnica de Catalunya
pp. 375
Session 6.2 Test Compaction

Independent Test Sequence Compaction through Integer Programming (Abstract)

Yiorgos Makris , Yale University
Petros Drineas , Rensselaer Polytechnic Institute
pp. 380

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume (Abstract)

Krishnendu Chakrabarty , Duke University
Seiji Kajihara , Kyushu Institute of Technology
Yasumi Doi , Kyushu Institute of Technology
Lei Li , Duke University
pp. 387

Static Test Compaction for Multiple Full-Scan Circuits (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 393

A Method to Find Don?t Care Values in Test Sequences for Sequential Circuits (Abstract)

Shin-ya Kobayashi , Ehime University
Seiji Kajihara , Kyusyu Institute of Technology
Yoshinobu Higami , Ehime University
Yuzo Takamatsu , Ehime University
Irith Pomeranz , Purdue University
pp. 397
Session 6.3 Invited Session: Techniques for Synthesizing into Fabrics

Simplifying SoC design with the Customizable Control Processor Platform (PDF)

Mark Kautzman , IBM Corporation
Bob Lynch , IBM Corporation
Richard Ray , IBM Corporation
Reinaldo Bergamaschi , IBM Corporation
Robert Devins , IBM Corporation
C. Ross Ogilvie , IBM Corporation
Santosh Gaur , IBM Corporation
Michael Hale , IBM Corporation
pp. 402

Structured ASICs: Opportunities and Challenges (Abstract)

Behrooz Zahiri , Magma Design Automation
pp. 404
Session 7.1 Hardware Partitioning

Multiple-V<sub>dd</sub> Scheduling/Allocation for Partitioned Floorplan (Abstract)

Dongku Kang , Purdue University
Mark C. Johnson , Purdue University
Kaushik Roy , Purdue University
pp. 412
Session 7.2 Energy-Aware Design and Application

KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths (Abstract)

Srinivas Katkoori , University of South Florida, Tampa
Chandramouli Gopalakrishnan , University of South Florida, Tampa
pp. 430

Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling (Abstract)

Sunil K. Chappidi , University of South Florida, Tampa
N. Ranganathan , University of South Florida, Tampa
Saraju P. Mohanty , University of South Florida, Tampa
pp. 441

An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks (Abstract)

Farhad Ghasemi-Tari , Univ. of Southern California, Los Angeles
Peng Rong , Univ. of Southern California, Los Angeles
Massoud Pedram , Univ. of Southern California, Los Angeles
pp. 444
Session 7.3 Invited Session: High-Speed Design Issues and Test Challenges

CMOS High-Speed I/Os - Present and Future (Abstract)

John Edmondson , Velio Communications, Inc.
Ramin Farjad-Rad , Velio Communications, Inc.
John Poulton , Velio Communications, Inc.
Ramesh Senthinathan , Velio Communications, Inc.
M.-J. Edward Lee , Velio Communications, Inc.
Hiok-Tiaq Ng , Velio Communications, Inc.
William J. Dally , Stanford University; Velio Communications, Inc.
pp. 454

Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors (Abstract)

G. Asmanis , Intel Corporation
K.W. Glass , Intel Corporation
S. Seetharaman , Intel Corporation
H.V. Duong , Intel Corporation
C. Bil , Intel Corporation
K. Kiziloglu , Intel Corporation
pp. 462
Session 8.1 Efficiency and Reliability

Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems (Abstract)

Bumsoo Kim , SAMSUNG Electronics, Co., Ltd.
Dongyoung Seo , SAMSUNG Electronics, Co., Ltd.
Shinhan Kim , SAMSUNG Electronics, Co., Ltd.
Chanik Park , SAMSUNG Electronics, Co., Ltd.
Jaeyu Seo , SAMSUNG Electronics, Co., Ltd.
pp. 474

Exploiting Microarchitectural Redundancy For Defect Tolerance (Abstract)

Charles R. Moore , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Premkishore Shivakumar , The University of Texas at Austin
pp. 481

Reducing Multimedia Decode Power using Feedback Control (Abstract)

John Lach , University of Virginia, Charlottesville
Kevin Skadron , University of Virginia, Charlottesville
Mircea Stan , University of Virginia, Charlottesville
Zhijian Lu , University of Virginia, Charlottesville
pp. 489
Session 8.2 Novel Methods in Logic Synthesis

Structural Detection of Symmetries in Boolean Functions (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley, CA
Guoqiang Wang , University of California at Berkeley, CA
Andreas Kuehlmann , University of California at Berkeley, CA; Cadence Berkeley Labs, Berkeley, CA
pp. 498

Boolean Decomposition Based on Cyclic Chains (Abstract)

Johan Karlsson , Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
Maxim Teslenko , Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
Elena Dubrova , Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
pp. 504

SAT-Based Algorithms for Logic Minimization (Abstract)

Samir Sapra , Carnegie Mellon University, Pittsburgh, PA
Michael Theobald , Carnegie Mellon University, Pittsburgh, PA
Edmund Clarke , Carnegie Mellon University, Pittsburgh, PA
pp. 510
Session 9.1 Communications and Context Management

Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels (Abstract)

Anand Selvarathinam , Texas A&M University
Euncheol Kim , Texas A&M University
Gwan Choi , Texas A&M University
pp. 520

Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches (Abstract)

Sudeep Pasricha , University of California, Irvine
Alex Veidenbaum , University of California, Irvine
pp. 526

Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files (Abstract)

Linda M. Wills , Georgia Institute of Technology, Atlanta
Santithorn Bunchua , Georgia Institute of Technology, Atlanta
D. Scott Wills , Georgia Institute of Technology, Atlanta
pp. 532

xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs (Abstract)

Davide Bertozzi , University of Bologna, DEIS
Luca Benini , University of Bologna, DEIS
Luca Giovannini , University of Bologna, DEIS
Matteo Dall'Osso , University of Bologna, DEIS
Gianluca Biccari , University of Bologna, DEIS
pp. 536
Session 9.2 Board Test and Power-Aware Test

Aggressive Test Power Reduction Through Test Stimuli Transformation (Abstract)

Alex Orailoglu , University of California, San Diego
Ozgur Sinanoglu , University of California, San Diego
pp. 542

Power-Time Tradeoff in Test Scheduling for SoCs (Abstract)

James Chin , The University of Texas at Dallas
Mehrdad Nourani , The University of Texas at Dallas
pp. 548

Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity (Abstract)

M. Nourani , The University of Texas at Dallas, Richardson
N. Ahmed , The University of Texas at Dallas, Richardson
M. H. Tehranipour , The University of Texas at Dallas, Richardson
pp. 554

Author Index (PDF)

pp. 561
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