A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits
2012 IEEE 30th International Conference on Computer Design (ICCD) (2003)
San Jose, California
Oct. 13, 2003 to Oct. 15, 2003
Ranga Vemuri , University of Cincinnati, OH
Madhubanti Mukherjee , University of Cincinnati, OH
Traditional application specific synthesis systems for DSP rely on a predesigned library of components. Designs in the DSP domain often involve constant operands. Using off-the-shelf library components for such designs can be wasteful in terms of area, power and timing. Operations involving constant operands are possible candidates for reduction based on partial evaluation. Classical logic synthesis is often incapable of performing reductions because of component sharing (typically decided during high level synthesis) between regular operations and those involving constant operands, which prevent minimizations during this phase. In this paper we propose a methodology for performing on-demand component reduction using partial evaluation during synthesis of application specific DSP circuits. The simplified components have better characteristics compared to their unreduced counterparts in terms of both delay and power. Use of reduced components in the synthesis loop showed a system wide improvement in performance, area and power for the synthesized designs for a variety of benchmark DSP circuits.
Ranga Vemuri, Madhubanti Mukherjee, "A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits", 2012 IEEE 30th International Conference on Computer Design (ICCD), vol. 00, no. , pp. 436, 2003, doi:10.1109/ICCD.2003.1240936