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2012 IEEE 30th International Conference on Computer Design (ICCD) (2003)
San Jose, California
Oct. 13, 2003 to Oct. 15, 2003
ISSN: 1063-6404
ISBN: 0-7695-2025-1
pp: 261
Daniel Eckerbert , Chalmers University of Technology, Sweden
Lars "J." Svensson , Chalmers University of Technology, Sweden
Per Larsson-Edefors , Chalmers University of Technology, Sweden
ABSTRACT
We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover, circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.
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CITATION
Daniel Eckerbert, Lars "J." Svensson, Per Larsson-Edefors, "A Mixed-Mode Delay-Locked-Loop Architecture", 2012 IEEE 30th International Conference on Computer Design (ICCD), vol. 00, no. , pp. 261, 2003, doi:10.1109/ICCD.2003.1240904
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