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Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors (2002)
Freiburg, Germany
Sept. 16, 2002 to Sept. 18, 2002
ISSN: 1063-6404
ISBN: 0-7695-1700-5
TABLE OF CONTENTS
Introduction

Welcome to ICCD (PDF)

pp. xiii
Keynote Addresses

From IP to Platforms (PDF)

Raul Camposano , Synopsys
pp. xix
Session 1.1: Special Invited Session: Computers in Media, Mobile and Servers

Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture (Abstract)

Atsushi Mizuno , Toshiba Corporation
Kazuyoshi Kohno , Toshiba Corporation
Ryuichiro Ohyama , Toshiba Corporation
Takahiro Tokuyoshi , Toshiba Corporation
Hironori Uetani , Toshiba Corporation
Hans Eichel , Toshiba Electronics Europe GmbH
Takashi Miyamori , Toshiba Corporation
Nobu Matsumoto , Toshiba Corporation
Masataka Matsui , Toshiba Corporation
pp. 2

Power-Constrained Microprocessor Design (Abstract)

H. Peter Hofstee , IBM Microelectronics
pp. 14
Session 1.2: Physical Design

A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect (Abstract)

Chung-Seok Seo , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 24

Physical Planning Of On-Chip Interconnect Architectures (Abstract)

Hongyu Chen , University of California at Dan Diego
Bo Yao , University of California at Dan Diego
Feng Zhou , University of California at Dan Diego
Chung-Kuan Cheng , University of California at Dan Diego
pp. 30

GPE: A New Representation for VLSI Floorplan Problem (Abstract)

Chang-Tzu Lin , Feng Chia University
De-Sheng Chen , Feng Chia University
Yi-Wen Wang , Feng Chia University
pp. 42

A Standard-Cell Placement Tool for Designs with High Row Utilization (Abstract)

Xiaojian Yang , University of California at Los Angeles
Bo-Kyung Choi , University of California at Los Angeles
Majid Sarrafzadeh , University of California at Los Angeles
pp. 45
Session 1.3: Verification

k-time Forced Simulation: A Formal Verification Technique for IP Reuse (Abstract)

Partha S. Roop , University of Auckland
A. Sowmya , University of New South Wales
S. Ramesh , Indian Institute of Technology at Bombay
pp. 50

Checking Equivalence for Circuits Containing Incompletely Specified Boxes (Abstract)

Christoph Scholl , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
pp. 56

Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering (Abstract)

Fadi A. Aloul , University of Michigan
Igor L. Markov , University of Michigan
Karem A. Sakallah , University of Michigan
pp. 64

Environment Synthesis for Compositional Model Checking (Abstract)

Hong Peng , Concordia University
Yassine Mokhtari , Concordia University
Sofiène Tahar , Concordia University
pp. 70
Session 2.1: Special Invited Session: Design ITRS 2001 — Issues and Solutions

Physical Design Challenges for Billion Transistor Chips (Abstract)

Patrick R. Groeneveld , Eindhoven University of Technology
pp. 78

From ASIC to ASIP: The Next Design Discontinuity (Abstract)

Kurt Keutzer , University of California at Berkeley
Sharad Malik , Princeton University
A. Richard Newton , University of California at Berkeley
pp. 84

High Level Functional Verification Closure (Abstract)

Surrendra Dudani , Synopsys, Inc.
Jayant Nagda , Synopsys, Inc.
pp. 91
Session 2.2: Data Path Elements for Multi-GHz Design

A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors (Abstract)

Oguz Ergin , State University of New York at Binghamton
Kanad Ghose , State University of New York at Binghamton
Gurhan Kucuk , State University of New York at Binghamton
Dmitry Ponomarev , State University of New York at Binghamton
pp. 118

Analysis of Blocking Dynamic Circuits (Abstract)

Tyler Thorp , University of Washington
Dean Liu , Stanford University
pp. 122
Session 2.3: Multimedia and Arithmetic

Parallel Multiple-Symbol Variable-Length Decoding (Abstract)

Jari Nikara , Tampere University of Technology
Stamatis Vassiliadis , Technical University of Delft
Jarmo Takala , Tampere University of Technology
Mihai Sima , Technical University of Delft
Petri Liuha , Nokia Research Center
pp. 126

Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm (Abstract)

J.-A. Piñeiro , Universidad Santiago de Compostela
M. D. Ercegovac , University of California at Los Angeles
J. D. Bruguera , Universidad Santiago de Compostela
pp. 132

Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable Functional Caches (RFCs) (Abstract)

Huesung Kim , Iowa State University
Arun K. Somani , Iowa State University
Akhilesh Tyagi , Iowa State University
pp. 138

Floating-Point Fused Multiply-Add with Reduced Latency (Abstract)

Tomas Lang , University of California at Irvine
Javier D. Bruguera , University of Santiago de Compostela
pp. 145
Session 3.1: Methodology Issues for High Performance Designs

Timing Window Applications in UltraSPARC-IIIi™ Microprocessor Design (Abstract)

Rita Yu Chen , Sun Microsystems, Inc.
Paul Yip , Sun Microsystems, Inc.
Georgios Konstadinidis , Sun Microsystems, Inc.
Andrew Demas , Sun Microsystems, Inc.
Fabian Klass , Sun Microsystems, Inc.
Rob Mains , Sun Microsystems, Inc.
Margaret Schmitt , Sun Microsystems, Inc.
Dina Bistry , Sun Microsystems, Inc.
pp. 158

A System-Level Solution to Domino Synthesis with 2 GHz Application (Abstract)

B. Chappell , Intel Corporation
X. Wang , Intel Corporation
P. Patra , Intel Corporation
P. Saxena , Intel Corporation
J. Vendrell , Intel Corporation
S. Gupta , Intel Corporation
S. Varadarajan , Intel Corporation
W. Gomes , Intel Corporation
S. Hussain , Intel Corporation
H. Krishnamurthy , Intel Corporation
M. Venkateshmurthy , Intel Corporation
S. Jain , Intel Corporation
pp. 164
Session 3.2: Low-Power Microarchitecture

Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study (Abstract)

Hongbo Yang , University of Delaware
R. Govindarajan , Indian Institute of Science at Bangalore
Guang R. Gao , University of Delaware
Kevin B. Theobald , University of Delaware
pp. 174

Balancing the Interconnect Topology for Arrays of Processors between Cost and Power (Abstract)

Esther Y. Cheng , University of California at San Diego
Feng Zhou , University of California at San Diego
Bo Yao , University of California at San Diego
Chung-Kuan Cheng , University of California at San Diego
Ronald Graham , University of California at San Diego
pp. 180

A Low Energy Set-Associative I-Cache with Extended BTB (Abstract)

Koji Inoue , Fukuoka University
Vasily G. Moshnyaga , Fukuoka University
Kazuaki Murakami , Kyushu University
pp. 187
Session 3.3: Design for Testability

Don't-Care Identification on Specific Bits of Test Patterns (Abstract)

Kohei Miyase , Kyusyu Institute of Technology
Seiji Kajihara , Kyusyu Institute of Technology
Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 194

An Extended Class of Sequential Circuits with Combinational Test Generation Complexity (Abstract)

Michiko Inoue , Nara Institute of Science and Technology
Chikateru Jinno , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 200

A Test Processor Concept for Systems-on-a-Chip (Abstract)

C. Galke , Brandenburg University of Technology Cottbus
M. Pflanz , IBM Deutschland Entwicklung GmbH
H. T. Vierhaus , Brandenburg University of Technology Cottbus
pp. 210
Session 4.1: Special Invited Session: Sensor Networks: New Architecture and Synthesis Challenges

Locating Tiny Sensors in Time and Space: A Case Study (Abstract)

Lewis Girod , University of Califnornia at Los Angeles
Vladimir Bychkovskiy , University of Califnornia at Los Angeles
Jeremy Elson , University of Califnornia at Los Angeles
Deborah Estrin , University of Califnornia at Los Angeles
pp. 214

A Distributed Computation Platform for Wireless Embedded Sensing (Abstract)

Andreas Savvides , University of California at Los Angeles
Mani B. Srivastava , University of California at Los Angeles
pp. 220

System-Architectures for Sensor Networks Issues, Alternatives, and Directions (Abstract)

Jessica Feng , University of California at Los Angeles
Farinaz Koushanfar , University of California at Berkeley
Miodrag Potkonjak , University of California at Los Angeles
pp. 226
Session 4.2: Computer Systems Design and Applications I

Subword Sorting with Versatile Permutation Instructions (Abstract)

Zhijie Shi , Princeton University
Ruby B. Lee , Princeton University
pp. 234

Performance Enhancements to the Active Memory System (Abstract)

Witawas Srisa-an , University of Nebraska at Lincoln
Chia-Tien Dan Lo , University of Texas at San Antonio
J. Morris Chang , Iowa State University
pp. 249
Session 4.3: Analog Test and Dependability

Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits (Abstract)

Sule Ozev , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 258

Accurate and Efficient Static Timing Analysis with Crosstalk (Abstract)

I-De Huang , University of Southern California
Sandeep K. Gupta , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 265

On the Detectability of Parametric Faults in Analog Circuits (Abstract)

Jacob Savir , New Jersey Institute Of Technology
Zhen Guo , New Jersey Institute Of Technology
pp. 273

Using Offline and Online BIST to Improve System Dependability — The TTPC-C Example (Abstract)

Andreas Steininger , Vienna University of Technology
Johann Vilanek , Vienna University of Technology
pp. 277
Session 5.1: Special Session: The Imagine Processor

The Imagine Stream Processor (Abstract)

Ujval J. Kapasi , Stanford University
William J. Dally , Stanford University
Scott Rixner , Rice University
John D. Owens , Stanford University
Brucek Khailany , Stanford University
pp. 282

VLSI Design and Verification of the Imagine Processor (Abstract)

Brucek Khailany , Stanford University
William J. Dally , Stanford University
Andrew Chang , Stanford University
Ujval J. Kapasi , Stanford University
Jinyung Namkoong , Stanford University
Brian Towles , Stanford University
pp. 289

Media Processing Applications on the Imagine Stream Processor (Abstract)

John D. Owens , Stanford University
Scott Rixner , Rice University
Ujval J. Kapasi , Stanford University
Peter Mattson , Stanford University
Brian Towles , Stanford University
Ben Serebrin , Stanford University
William J. Dally , Stanford University
pp. 295

A Stream Processor Development Platform (Abstract)

Ben Serebrin , Stanford University
John D. Owens , Stanford University
Chen H. Chen , University of Southern California
Stephen P. Crago , University of Southern California
Ujval J. Kapasi , Stanford University
Peter Mattson , Stanford University
Jinyung Namkoong , Stanford University
Scott Rixner , Rice University
William J. Dally , Stanford University
pp. 303
Session 5.2: Low Power Circuit Techniques

On The Impact of Technology Scaling On Mixed PTL/Static Circuits (Abstract)

Geun Rae Cho , Colorado State University
Tom Chen , Hewlett Packard Co.
pp. 322

Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits (Abstract)

Shanq-Jang Ruan , National Taiwan University
Edwin Naroska , University of Dortmund
Chia-Lin Ho , National Taiwan University
Feipei Lai , National Taiwan University
pp. 327
Session 5.3: Cache Memories

Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost (Abstract)

Yen-Jen Chang , National Taiwan University
Feipei Lai , National Taiwan University
Shanq-Jang Ruan , National Taiwan University
pp. 334

A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors (Abstract)

Jinwoo Kim , Georgia Institute of Technology
Krishna V. Palem , Georgia Institute of Technology
Weng-Fai Wong , National University of Singapore
pp. 340

Trace Cache Performance Parameters (Abstract)

Afzal Hossain , Syracuse University
Daniel J. Pease , Syracuse University
James S. Burns , Syracuse University
Nasima Parveen , Syracuse University
pp. 348

Data Cache Design Considerations for the Itanium? 2 Processor (Abstract)

Terry Lyon , Hewlett-Packard
Eric Delano , Hewlett-Packard
Cameron McNairy , Intel Corporation
Dean Mulla , Intel Corporation
pp. 356
Session 6.1: Special Invited Session: Processors in Automotive Systems

Automotive Virtual Integration Platforms: Why?s, What?s, and How?s (Abstract)

Paolo Giusto , Cadence Design Systems
Jean-Yves Brunel , Cadence Design Systems
Alberto Ferrari , Parades GEIE
Eliane Fourgeau , Cadence Design Systems
Luciano Lavagno , Cadence Design Systems
pp. 370

Models of IP?s for Automotive Virtual Integration Platforms (PDF)

Paolo Giusto , Cadence Design Systems
Jean-Yves Brunel , Cadence Design Systems
Alberto Ferrari , Parades EEIG
Eliane Fourgeau , Cadence Design Systems
Luciano Lavagno , Cadence Design Systems
Barry Orourke , Cadence Design Systems
Emanuele Guasto , Parades EEIG
pp. 379
Session 6.2: Power Management and High Level Synthesis

Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes (Abstract)

D. Duarte , Intel Corporation
N. Vijaykrishnan , Pennsylvania State University
M.J. Irwin , Pennsylvania State University
H-S Kim , Pennsylvania State University
G. McFarland , Intel Corporation
pp. 382

Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors (Abstract)

Lin Zhong , Princeton University
Jiong Luo , Princeton University
Yunsi Fei , Princeton University
Niraj K. Jha , Princeton University
pp. 391

Accelerated SAT-based Scheduling of Control/Data Flow Graphs (Abstract)

Seda Ogrenci Memik , University of California at Los Angeles
Farzan Fallah , Fujitsu Laboratories of America, Inc.
pp. 395
Session 6.3: Speculative and Packet Oriented Architectures

Trace-Level Speculative Multithreaded Architecture (Abstract)

Carlos Molina , Universitat Rovira i Virgili
Antonio González , Universitat Polit?cnica de Catalunya
Jordi Tubella , Universitat Polit?cnica de Catalunya
pp. 402

Speculative Trace Scheduling in VLIW Processors (Abstract)

Manvi Agarwal , Indian Institute of Science at Bangalore
S. K. Nandy , Indian Institute of Science at Bangalore
J.v. Eijndhoven , Philips Research Laboratories
S. Balakrishnan , Philips Research Laboratories
pp. 408

Embedded Protocol Processor for Fast and Efficient Packet Reception (Abstract)

Tomas Henriksson , Link?pings Universitet
Ulf Nordqvist , Link?pings Universitet
Dake Liu , Link?pings Universitet
pp. 414
Session 7.1: Interconnect Modeling and Analysis

Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model (Abstract)

Arif Ishaq Abou-Seido , Intel Corporation
Brian Nowak , IBM Corporation
Chris Chu , Iowa State University
pp. 422

Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques (Abstract)

Haitian Hu , University of Minnesota
Sachin S. Sapatnekar , University of Minnesota
pp. 434
Session 7.2: Issues in Processor Architecture

Applying Decay Strategies to Branch Predictors for Leakage Energy Savings (Abstract)

Zhigang Hu , Princeton University
Philo Juang , Princeton University
Kevin Skadron , University of Virginia
Douglas Clark , Princeton University
Margaret Martonosi , Princeton University
pp. 442

Dynamic Loop Caching Meets Preloaded Loop Caching — A Hybrid Approach (Abstract)

Ann Gordon-Ross , University of California at Riverside
Frank Vahid , University of California at Riverside and University of California at Irvine
pp. 446

Adaptive Pipeline Depth Control for Processor Power-Management (Abstract)

Aristides Efthymiou , University of Manchester
Jim D. Garside , University of Manchester
pp. 454

Improving Processor Performance by Simplifying and Bypassing Trivial Computations (Abstract)

Joshua J. Yi , University of Minnesota - Twin Cities
David J. Lilja , University of Minnesota - Twin Cities
pp. 462
Session 7.3: Low Power Test, Diagnosis

A Low Power Pseudo-Random BIST Technique (Abstract)

Nadir Z. Basturkmen , University of Iowa
Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
pp. 468

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding (Abstract)

Paul M. Rosinger , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
Nicola Nicolici , McMaster University
pp. 474

Fault Dictionary Size Reduction through Test Response Superposition (Abstract)

Baris Arslan , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 480
Session 8.1: System Design Issues

Designing an Asynchronous Microcontroller Using Pipefitter (Abstract)

Ivan Blunno , Politecnico di Torino
Luciano Lavagno , Politecnico di Torino
pp. 488

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip (Abstract)

L. Benini , Università di Bologna
D. Bertozzi , Università di Bologna
D. Bruni , Università di Bologna
N. Drago , Università di Verona
F. Fummi , Università di Verona
M. Poncino , Università di Verona
pp. 494

A Design Methodology for Application-Specific Real-Time Interfaces (Abstract)

S. Ihmor , Paderborn University
M. Visarius , Paderborn University
W. Hardt , Paderborn University
pp. 500
Session 8.2: Computer Systems Design and Applications II

TAXI: Trace Analysis for X86 Interpretation (Abstract)

Stevan Vlaovic , Sun Microsystems
Edward S. Davidson , University of Michigan
pp. 508

Embedded Operating System Energy Analysis and Macro-Modeling (Abstract)

T. K. Tan , Princeton University
N. K. Jha , Princeton University
pp. 515

SIMD Extension to VLIW Multicluster Processors for Embedded Applications (Abstract)

Domenico Barretta , Politecnico di Milano
William Fornaciari , Politecnico di Milano
Mariagiovanna Sami , Politecnico di Milano
Danilo Pau , STMicroelectronics S.r.l.
pp. 523

JMA: The Java-Multithreading Architecture for Embedded Processors (Abstract)

Panit Watcharawitch , University of Cambridge
Simon Moore , University of Cambridge
pp. 527
Author Index

Author Index (PDF)

pp. 531
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