The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (2001)
Austin, Texas
Sept. 23, 2001 to Sept. 26, 2001
ISBN: 0-7695-1200-3

Welcome to ICCD (PDF)

pp. xiii
Keynote Addresses
Session 1.1: Asynchronous Techniques

Arithmetic Logic Circuits using Self-Timed Bit Level Dataflow and Early Evaluation (Abstract)

Cherrice Traver , Union College
Robert B. Reese , Mississippi State University
Mitch A. Thornton , Mississippi State University
pp. 0018
Session 1.2: Embedded Tutorial
Session 1.3: Architectural Modeling: Performance and Power Analysis

Minimal Subset Evaluation : Rapid Warm-Up for Simulated Hardware State (Abstract)

John W. Haskins Jr , University of Virginia
Kevin Skadron , University of Virginia
pp. 0032

A Framework for Energy Estimation of VLIW Architecture (Abstract)

M. J. Irwin , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
H. S. Kim , The Pennsylvania State University
pp. 0040

High-Level Power Modeling of CPLDs and FPGAs (Abstract)

Li Shang , Princeton University
Niraj K. Jha , Princeton University
pp. 0046
Session 2.1: Caching

Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores (Abstract)

Konrad Lai , Intel Corporation
Lu Peng , University of Florida
Qianrong Ma , Oracle Corporation
Jih-Kwon Peir , University of Florida
pp. 0054

In-Line Interrupt Handling for Software-Managed TLBs (Abstract)

Aamer Jaleel , University of Maryland at College Park
Bruce Jacob , University of Maryland at College Park
pp. 0062

Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures (Abstract)

Weiyu Tang , University of California, Irvine
Rajesh Gupta , University of California, Irvine
Alexandru Nicolau , University of California, Irvine
pp. 0068
Session 2.2: Simulation Based Verification

A New Functional Test Program Generation Methodology (Abstract)

Farzan Fallah , Fujitsu Labs. of America, Inc.
Koichiro Takayama , Fujitsu Labs. of America, Inc.
pp. 0076

A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage (Abstract)

David G. Chinnery , University of California, Berkeley
Kurt Keutzer , University of California, Berkeley
Serdar Tasiran , Compaq Systems Research Center
Scott J. Weber , University of California, Berkeley
Farzan Fallah , Fujitsu Labs of America, Inc.
pp. 0082

Selecting a Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division (Abstract)

David W. Matula , Southern Methodist University
Lee D. McFearin , Southern Methodist University
pp. 0089
Session 2.3: Modeling of Capacitance and Crosstalk Noise

Linear Time Hierarchical Capacitance Extraction without Multipole Expansion (Abstract)

Yu-Min Lee , University of Wisconsin-Madison
Saisanthosh Balakrishnan , University of Wisconsin-Madison
Hyungsuk Kim , University of Wisconsin-Madison
Charlie C.-P. Chen , University of Wisconsin-Madison
Jong Hyuk Park , University of Wisconsin-Madison
pp. 0098

Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits (Abstract)

Payam Heydari , University of California, Irvine
Massoud Pedram , University of Southern California
pp. 0104

Crosstalk Noise Estimation for Generic RC Trees (Abstract)

Masao Takahashi , Kyoto University
Masanori Hashimoto , Kyoto University
Hidetoshi Onodera , Kyoto University
pp. 0110
Session 3.1: Improving the Performance of Caching Structures

A Banked-Promotion TLB for High Performance and Low Power (Abstract)

Seh-Woong Jeong , Samsung Electronics Co., Ltd.
Shin-Dug Kim , Yonsei University
Jung-Hoon Lee , Yonsei University
Jang-Soo Lee , Yonsei University
pp. 0118

Filtering Superfluous Prefetches Using Density Vectors (Abstract)

Thomas R. Puzak , IBM Corporation T. J. Watson Research Center
Wei-Fen Lin , University of Michigan
Doug Burger , University of Texas at Austin
Steven K. Reinhardt , University of Michigan
pp. 0124

Allocation by Conflict: A Simple, Effective Multilateral Cache Management Scheme (Abstract)

Edward S. Davidson , The University of Michigan
Edward S. Tam , Apple Computer, Inc.
Gary S. Tyson , The University of Michigan
Stevan A. Vlaovic , The University of Michigan
pp. 0133
Session 3.2: Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
Session 3.3: Invited Session: Power 4 Microprocessor- Organizer: J. M. Tendler

Session Abstract (PDF)

pp. 0161
Session 4.1: Embedded Tutorial
Session 4.2: Computer Arithmetic

Improved ZDN-Arithmetic for Fast Modulo Multiplication (Abstract)

Dirk Timmermann , University of Rostock
Hagen Ploog , University of Rostock
Sebastian Flügel , University of Rostock
pp. 0166

Design Alternatives for Parallel Saturating Multioperand Adders (Abstract)

John Glossner , Sandbridge Technologies
Michael J. Schulte , Lehigh University
Erdem Hokenek , Sandbridge Technologies
Pablo I. Balzola , Lehigh University
Jie Ruan , Lehigh University
pp. 0172
Session 4.3: Circuit Sizing and Optimization

Gate Sizing to Eliminate Crosstalk Induced Timing Violation (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Tong Xiao , Sun Microsystems, Inc.
pp. 0186

Performance Optimization by Wire and Buffer Sizing under the Transmission Line Model (Abstract)

Tai-Chen Chen , National Taiwan University
Yao-Wen Chang , National Taiwan University
Song-Ra Pan , National Chiao Tung University
pp. 0192
Session 5.1: Clocking and Time-Domain Measurements

Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective (Abstract)

Payam Heydari , University of California, Irvine
Massoud Pedram , University of Southern California
pp. 0209

On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs (Abstract)

Martin Saint-Laurent , Intel Corporation
James D. Meindl , Georgia Institute of Technology
Madhavan Swaminathan , Georgia Institute of Technology
pp. 0214
Session 5.2: Processor Microarchitecture

Selective Branch Prediction Reversal by Correlating with Data Values and Control Flow (Abstract)

José M. García , Universidad de Murcia
Antonio González , Universitat Polit?cnica de Catalunya
José González , Universidad de Murcia
Juan L. Aragón , Universidad de Murcia
pp. 0228

Mutable Functional Units and Their Applications on Microprocessors (Abstract)

Yong Luo , Intel Corporation
Yan Solihin , University of Illinois at Urbana-Champaign
Dominique Lavenier , IRISA/CNRS
Kirk W. Cameron , University of South Carolina
Maya Gokhale , Los Alamos National Laboratory
pp. 0234

Compiler-Directed Classification of Value Locality Behavior (Abstract)

Qing Zhao , Univ. of Minnesota
David J. Lilja , Univ. of Minnesota
pp. 0240
Session 5.3: Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics

Designing Circuits for Disk Drives (Abstract)

Georg Pelz , Infineon Technologies, Memory Products, Network and Computer Storage
pp. 0256

Hard Disk Controller: The Disk Drive's Brain and Body (Abstract)

James Jeppesen , Infineon Technologies; Memory Products, Network and Computer Storage
Walt Allen , Infineon Technologies; Memory Products, Network and Computer Storage
Steve Anderson , Infineon Technologies; Memory Products, Network and Computer Storage
Michael Pilsl , Infineon Technologies; Memory Products, Network and Computer Storage
pp. 0262

Motion-Control: The Power Side of Disk Drives (Abstract)

W. Sereinig , Infineon Technologies, Memory Products, Network and Computer Storage
pp. 0268
Session 6.1: Energy Efficiency Caches and Multiport Cache Structures

Static Energy Reduction Techniques for Microprocessor Caches (Abstract)

Heather Hanson , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
M.S. Hrishikesh , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Vikas Agarwal , The University of Texas at Austin
pp. 0276

Parallel Cachelets (Abstract)

John P. Shen , Intel Corporation
Ryan Rakvic , Intel Corporation
Deepak Limaye , Carnegie Mellon University
pp. 0284
Session 6.2: Control by Simulation and On-line Checking

High Performance Parallel Fault Simulation (Abstract)

Brion Keller , IBM Corp.
Eric Skuldt , IBM Corp.
Bapiraju Vinnakota , University of Minnesota,
Amit K. Varshney , Intel Corporation
pp. 0308

On-Line Integrity Monitoring of Microprocessor Control Logic (Abstract)

Arun K. Somani , Iowa State University
Seongwoo Kim , Iowa State University
pp. 0314
Session 6.3: CAD Algorithms for Physical Design

A Timing-Driven Macro-Cell Placement Algorithm (Abstract)

Robert K. Brayton , University of California, Berkeley
Abdallah Tabbara , University of California, Berkeley
Fan Mo , University of California, Berkeley
pp. 0322

Fixed-Outline Floorplanning through Better Local Search (Abstract)

Saurabh N. Adya , Univ. of Michigan
Igor L. Markov , Univ. of Michigan
pp. 0328

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning (Abstract)

Jai-Ming Lin , National Chiao Tung University
Mango C.-T. Chao , National Chiao Tung University
Guang-Ming Wu , Nan-Hua University
Yao-Wen Chang , National Taiwan University
pp. 0335
Panel Discussion
Session 7.1: Invited Session: Network Processors

Session Abstract (PDF)

pp. 345
Session 7.2: Formal Methods for Property Verification and Equivalence Verification
Session 7.3: Hardware Representation

BDD Variable Ordering by Scatter Search (Abstract)

Xiaoyu Song , Portland State University
William N. N. Hung , Intel Corporation
pp. 0368

Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis (Abstract)

C.-J. Richard Shi , University of Washington
Alicia Manthe , University of Washington
pp. 0374

Run-Time Execution of Reconfigurable Hardware in a Java Environment (Abstract)

Demetris Galatopoullos , Northeastern University
Miriam Leeser , Northeastern University
Elias Manolakos , Northeastern University
Heather Quinn , Northeastern University
L.A. Smith King , College of the Holy Cross
pp. 0380
Session 8.1: Circuit Techniques

Realization of Multiple-Output Functions by Reconfigurable Cascades (Abstract)

Munehiro Matsuura , Kyushu Institute of Technology
Tsutomu Sasao , Kyushu Institute of Technology
Yukihiro Iguchi , Meiji University
pp. 0388

A Low-Power Cache Design for CalmRISC(tm)-Based Systems (Abstract)

Sangyeun Cho , Samsung Electronics Co.
Seh-Woong Jeong , Samsung Electronics Co.
Wooyoung Jung , Samsung Electronics Co.
Yongchun Kim , Samsung Electronics Co.
pp. 0394

Interconnect-Centric Array Architectures for Minimum SRAM Access Time (Abstract)

Stephen Kosonocky , IBM T. J. Watson Research Center
James D. Meindl , Georgia Institute of Technology
Azeez J. Bhavnagarwala , IBM T. J. Watson Research Center
pp. 0400

Understanding and Addressing the Noise Induced by Electrostatic Discharge in Multiple Power Supply Systems (Abstract)

Yoonjong Huh , LSI Logic Corporation
Jaesik Lee , Bell Labs, Lucent Technologies
Peter Bendix , LSI Logic Corporation
Sung-Mo (Steve) Kang , University of California
pp. 0406
Session 8.2: DSP/Multimedia

Cost-Effective Hardware Acceleration of Multimedia Applications (Abstract)

Lizy K. John , The University of Texas
Deependra Talla , The University of Texas
pp. 0415

MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-Augmented TriMedia Processor (Abstract)

Mihai Sima , Delft University of Technology and Philips Research
Stamatis Vassiliadis , Delft University of Technology
Kees Vissers , TriMedia Technologies
Jos T.J. Van Eijndhoven , Philips Research
Sorin Cotofana , Delft University of Technology
pp. 0425

Low-Energy DSP Code Generation Using a Genetic Algorithm (Abstract)

Rainer Leupers , University of Dortmund, Germany
Gerhard Fettweis , Technische Universit?t Dresden
Peter Marwedel , University of Dortmund, Germany
Thorsten Dräger , Technische Universit?t Dresden
Markus Lorenz , University of Dortmund, Germany
pp. 0431

Voltage Scaling for Energy Minimization with QoS Constraints (Abstract)

Ali Manzak , Arizona State University
Chaitali Chakrabarti , Arizona State University
pp. 0438
Session 8.3: Novel Architectures and ISA Extensions

Matching Architecture to Application via Configurable Processors: A Case Study with Boolean Satisfiability Problem (Abstract)

Conor F. Madigan , University of California at Berkeley
Matthew W. Moskewicz , University of California at Berkeley
Sharad Malik , Princeton University
Ying Zhao , Princeton University
Albert Wang , Tensilica Inc.
pp. 0447

3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis (Abstract)

Yoshiyuki Kaeriyama , Tohoku University
Tadao Nakamura , Tohoku University
Ken-ichi Suzuki , Miyagi National College of Technology
Kentaro Sano , Tohoku University
Hiroaki Kobayashi , Tohoku University
Nobuyuki Oba , IBM Japan, Ltd.
Yasumasa Saida , Tohoku University
pp. 0462

Use of Local Memory for Efficient Java Execution (Abstract)

M. Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
S. Tomar , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
S. Kim , Pennsylvania State University
pp. 0468
Poster Papers

An Analytical Model for Trace Cache Instruction Fetch Performance (Abstract)

Daniel J. Pease , Syracuse University
Afzal Hossain , Syracuse University
pp. 0477

Performance Driven Global Routing through Gradual Refinement (Abstract)

Sachin S. Sapatnekar , University of Minnesota
Jiang Hu , IBM Microelectronics
pp. 0481

Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement (Abstract)

Junaid A. Khan , King Fahd University of Petroleum and Minerals
Aiman El-Maleh , King Fahd University of Petroleum and Minerals
Habib Youssef , King Fahd University of Petroleum and Minerals
Sadiq M. Sait , King Fahd University of Petroleum and Minerals
pp. 0484

Fast Specification of Cycle-Accurate Processor Models (Abstract)

Alan J. Hu , University of British Columbia
Felix Sheng-Ho Chang , University of British Columbia
pp. 0488

A Performance Analysis of the Active Memory System (Abstract)

Witawas Srisa-an , Illinois Institute of Technology
J. Morris Chang , Illinois Institute of Technology
Chia-Tien Dan Lo , Illinois Institute of Technology
pp. 0493

An Algorithm for Dynamically Reconfigurable FPGA Placement (Abstract)

Jai-Ming Lin , National Chiao Tung University
Guang-Ming Wu , Nan-Hua University
Yao-Wen Chang , National Taiwan University
pp. 0501

Efficient Function Approximation for Embedded and ASIC Applications (Abstract)

James W. Hauser , University of Cincinnati
Carla N. Purdy , University of Cincinnati
pp. 0507

An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking (Abstract)

In-Cheol Park , Korea Advanced Institute of Science and Technology
Se-Hyeon Kang , Korea Advanced Institute of Science and Technology
Myoung-Cheol Shin , Korea Advanced Institute of Science and Technology
pp. 0511

A Heuristic for Multiple Weight Set Generation (Abstract)

Hong-Sik Kim , Yonsei University
Jin -kyue Lee , Yonsei University
Sungho Kang , Yonsei University
pp. 0513

Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem (Abstract)

J.L. White , Michigan State University
A.S. Wojcik , Michigan State University
M.-J. Chung , Michigan State University
T.E. Doom , Wright State University
pp. 0519

MCOMA: A Multithreaded COMA Architecture (Abstract)

Jean-Luc Gaudiot , University of Southern California
Halima El Naga , California State Polytechnic University
pp. 0523

Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors (Abstract)

Amita va Majumdar , SUN Microelectronics DFT Architecture Sunnyvale Design Center Sunnyvale
Kamran Zarrineh , SUN Microelectronics Millenium DFT Architecture Boston Design Center
Thomas A. Ziaja , SUN Microelectronics DFT Architecture Austin Design Center Austin
pp. 0526

Reducing Cache Pollution of Prefetching in a Small Data Cache (Abstract)

Pipat Reungsang , Iowa State University
Sun Kyu Park , Iowa State University
Hyung-Lae Roh , Samsung Electronics
Gyungho Lee , Iowa State University
Seh-Woong Jeong , Samsung Electronics
pp. 0530

Alloyed Path-Pattern Scheme for Branch Prediction (Abstract)

Gyungho Lee , Iowa State University
Rajesh Ramanujam , Iowa State University
Murali Ravirala , Iowa State University
pp. 0534

Timing Characterization of Dual-Edge Triggered Flip-Flops (Abstract)

Marko Aleksic , University of California Davis
Vojin G. Oklobdzija , University of California Davis
Nikola Nedovic , University of California Davis
pp. 0538

Performance Impact of Addressing Modes on Encryption Algorithms (Abstract)

Ruby B. Lee , Princeton University
A. Murat Fiskiran , Princeton University
pp. 0542

Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages (Abstract)

Yvon Savaria , ?cole Polytechnique de Montr?al
El Mostapha Aboulhamid , Universit? de Montr?al
Noureddine Chabini , Universit? de Montr?al
pp. 0546

Pre-Routing Estimation of Shielding for RLC Signal Integrity (Abstract)

Lei He , University of Wisconsin
James D. Z. Ma , University of Wisconsin
Arvind Parihar , University of Wisconsin
pp. 0553

Author Index (PDF)

pp. 0557
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