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2012 IEEE 30th International Conference on Computer Design (ICCD) (2000)
Austin, Texas
Sept. 17, 2000 to Sept. 20, 2000
ISSN: 1063-6404
ISBN: 0-7695-0801-4
TABLE OF CONTENTS

Chairs' Message (PDF)

pp. xii
Keynote Address
Session 1.1: New Architectures, Chair: Mauricio Breternitz, Motorola

Architectural Impact of Secure Socket Layer on Internet Servers (Abstract)

Krishna Kant , Intel Corporation
Prasant Mohapatra , Michigan State University
Ravishankar Iyer , Intel Corporation
pp. 7

Fast Subword Permutation Instructions Using Omega and Flip Network Stages (Abstract)

Ruby B. Lee , Princeton University
Xiao Yang , Princeton University
pp. 15
Session 1.2: Fault-Simulation and ATPG at Different Design Levels, Chair: Nur Touba, The University of Texas at Austin

Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping (Abstract)

Junwei Hou , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 35

Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds (Abstract)

Spyros Tragoudas , Southern Illinois University
Dimitri Kagaris , Southern Illinois University
pp. 42

An Application of Genetic Algorithms and BDDs to Functional Testing (Abstract)

Alessandro Fin , Universit? di Verona
Franco Fummi , Universit? di Verona
Fabrizio Ferrandi , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
pp. 48
Session 1.3: Advanced Design Techniques, Chair: Ken Shepard, Columbia University

High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology (Abstract)

Jaesik Lee , University of Illinois at Urbana-Champaign
Chulwoo Kim , University of Illinois at Urbana-Champaign
Sung-Mo (Steve) Kang , University of Illinois at Urbana-Champaign
Eric Martina , University of Illinois at Urbana-Champaign
Kwang-Hyun Baek , University of Illinois at Urbana-Champaign
pp. 59

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems (Abstract)

P.A. Cunningham , University of Cambridge
R.D. Mullins , University of Cambridge
G.S. Taylor , University of Cambridge
P. Robinson , University of Cambridge
S.W. Moore , University of Cambridge
pp. 73
Session 2.1: Improving CPU Performance, Chair: Brian Grayson, Motorola

Hybridizing and Coalescing Load Value Predictors (Abstract)

Martin Burtscher , University of Colorado
Benjamin G. Zorn , Microsoft
pp. 81

A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages (Abstract)

Yul Chu , University of British Columbia
M.R. Ito , University of British Columbia
pp. 93

Architectural Support for Dynamic Memory Management (Abstract)

J. Morris Chang , Illinois Institute of Technology
Chia-Tien Dan Lo , Illinois Institute of Technology
Witawas Srisa-an , Illinois Institute of Technology
pp. 99

SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing (Abstract)

Taisuke Boku , University of Tsukuba
Masaaki Kondo , University of Tokyo
Hideki Okawara , University of Tokyo
Hiroshi Nakamura , University of Tokyo
pp. 105
Session 2.2: Parasitic Modeling, Analysis, and Optimization, Chair: Tom Dillinger, Sun Microsystems

Worst Delay Estimation in Crosstalk Aware Static Timing Analysis (Abstract)

Tong Xiao , University of California at Santa Barbara
Malgorzata Marek-Sadowska , University of California at Santa Barbara
pp. 115

Analysis and Optimization of Ground Bounce in Digital CMOS Circuits (Abstract)

Payam Heydari , University of Southern California
Massoud Pedram , University of Southern California
pp. 121
Session 2.3: Low Power and Arithmetic, Chair: Margarida Jacome, The University of Texas at Austin

A Novel Low-Power Microprocessor Architecture (Abstract)

Yiannos Manoli , University of Saarland
Rolf Hakenes , University of Saarland
pp. 141

A Power Perspective of Value Speculation for Superscalar Microprocessors (Abstract)

Rafael Moreno , Universidad Complutense de Madrid
Luis Piñuel , Universidad Complutense de Madrid
Francisco Tirado , Universidad Complutense de Madrid
Silvia del Pino , Universidad Complutense de Madrid
pp. 147

Multilevel Reverse-Carry Adder (Abstract)

Toms Lang , University of California at Irvine
Javier D. Bruguera , University of Santiago de Compostela
pp. 155

Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures (Abstract)

Viktor Lapinskii , University of Texas at Austin
Brian L. Evans , University of Texas at Austin
Lizy K. John , University of Texas at Austin
Deependra Talla , University of Texas at Austin
pp. 163
Session 3.1: Servers and Parallelism, Chair: Ruby Lee, Princeton University

Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation (Abstract)

H. V. Jagadish , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
Qiang Cao , University of Illinois at Urbana-Champaign
pp. 175

Analysis of Shared Memory Misses and Reference Patterns (Abstract)

Jeffrey B. Rothman , Lyris Technologies, Inc.
Alan Jay Smith , University of California at Berkeley
pp. 187

Power-Sensitive Multithreaded Architecture (Abstract)

George Z.N. Cai , Intel Corporation
John S. Seng , University of California at San Diego
Dean M. Tullsen , University of California at San Diego
pp. 199
Session 3.2: Circuit Optimization and Analysis, Chair: Shervin Hojat, IBM

Buffer Library Selection (Abstract)

Charles J. Alpert , IBM Austin Research Laboratory
Stephen T. Quay , IBM Microelectronics
R. Gopal Gandham , IBM Microelectronics
Jose L. Neves , IBM Microelectronics
pp. 221
Session 3.3: Logic Circuit Families, Chair: Shyh-Jye Jou, National Central University

Current-Mode Threshold Logic Gates (Abstract)

I.N. Hajj , University of Illinois at Urbana-Champaign
S. Bobba , University of Illinois at Urbana-Champaign
pp. 235

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family (Abstract)

Kaushik Roy , Purdue University
Alexandre Solomatnikov , Purdue University
Dinesh Somasekhar , Intel Corp.
Cheng-Kok Koh , Purdue University
pp. 241

Output Prediction Logic: A High-Performance CMOS Design Technique (Abstract)

Carl Sechen , University of Washington
Larry McMurchie , University of Washington
Gin Yee , University of Washington
Tyler Thorp , University of Washington
Su Kio , University of Washington
pp. 247
Keynote Address
Session 4.1: Intelligent Memory, Chair: Steven Reinhardt, University of Michigan

A Study of Channeled DRAM Memory Architectures (Abstract)

Lars Friebe , University of Hannover
Yoshikazu Yabe , NEC Corp
Masato Motomura , NEC Corp
pp. 261

DRAM-Page Based Prediction and Prefetching (Abstract)

Haifeng Yu , Duke University
Gershon Kedem , Duke University
pp. 267

Reducing Cost and Tolerating Defects in Page-based Intelligent Memory (Abstract)

Lucian-Vlad Lita , University of California at Davis
Diana Keen , University of California at Davis
Mark Oskin , University of California at Davis
Justin Hensley , University of California at Davis
Frederic T. Chong , University of California at Davis
pp. 276
Session 4.2: Processor Microarchitecture, Chair: Steve Furber, The University of Manchester

A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval (Abstract)

Jang-Soo Lee , Yonsei University
Jung-Hoon Lee , Yonsei University
Shin-Dug Kim , Yonsei University
pp. 287

Design of Instruction Stream Buffer with Trace Support for X86 Processors (Abstract)

Jih-Ching Chiu , National Chiao Tung University
Chung-Ping Chung , National Chiao Tung University
I-Huan Huang , National Chiao Tung University
pp. 294

A Trace Based Evaluation of Speculative Branch Decoupling (Abstract)

Akhilesh Tyagi , Iowa State University
Anshuman S Nadkarni , Iowa State University
pp. 300
Session 4.3: Digital Logic Techniques, Chair: Barbara Chappell, Accelerant Networks

An Adder Using Charge Sharing and its Application in DRAMs (Abstract)

Jacob A. Abraham , University of Texas at Austin
Songjun Lee , University of Texas at Austin
Hak-soo Yu , University of Texas at Austin
pp. 311

Fixed-Width Multiplier for DSP Application (Abstract)

Shyh-Jye Jou , National Central University
Hui-Hsuan Wang , National Central University
pp. 318

Dynamic Flip-Flop with Improved Power (Abstract)

Vojin G. Oklobdzija , University of California at Davis
Nikola Nedovic , University of California at Davis
pp. 323
Session 5.1: Embedded Processors: Architecture and System-Design Issues, Chair: Ricardo Gonzales, Tensilica

Processors for Mobile Applications (Abstract)

Jan M. Rabaey , University of California at Berkeley
Vandana Prabhu , Tensilica, Inc.
Miodrag Potkonjak , University of California at Los Angeles
Farinaz Koushanfar , University of California at Los Angeles
pp. 603

AMULET3: A 100 MIPS Asynchronous Embedded Processor (Abstract)

J.D. Garside , University of Manchester
D.A. Edwards , University of Manchester
S.B. Furber , University of Manchester
pp. 329

Predictive Strategies for Low-Power RTOS Scheduling (Abstract)

Mani Srivastava , University of California at Los Angeles
Pavan Kumar , University of California at Los Angeles
pp. 343
Session 5.2: Floorplanning and Partitioning, Chair: Tim Burks, Magma Design Automation

Rectilinear Block Placement Using B*-Trees (Abstract)

Yun-Chih Chang , National Chiao Tung University
Guang-Ming Wu , National Chiao Tung University
Yao-Wen Chang , National Chiao Tung University
pp. 351

Fast Hierarchical Floorplanning with Congestion and Timing Control (Abstract)

A. Ranjan , Northwestern University
M. Sarrafzadeh , Northwestern University
K. Bazargan , Northwestern University
pp. 357

An Evaluation of Move-Based Multi-Way Partitioning Algorithms (Abstract)

Joan Carletta , University of Akron
Elie Yarack , Silicon Graphics, Inc.
pp. 363

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis (Abstract)

Koji Oohashi , Japan Advanced Institute of Science and Technology
Satoshi Tayu , Japan Advanced Institute of Science and Technology
Mineo Kaneko , Japan Advanced Institute of Science and Technology
pp. 370
Session 5.3: Basic Algorithms in Verification and Test, Chair: Yatin Hoskote, Intel

On Solving Stack-Based Incremental Satisfiability Problems (Abstract)

Jesse Whittemore , University of Michigan
Karen Sakallah , University of Michigan
Joonyoung Kim , University of Michigan
pp. 379

Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Stefan Höreth , Siemens AG
Wolfgang Günther , Albert-Ludwigs-University
pp. 383
Session 6.1: Special Session: Advancements in DSP Architecture

A Multi-Level Memory System Architecture for High-Performance DSP Applications (Abstract)

Dave Comisky , Texas Instruments Incorporated
Sanjive Agarwala , Texas Instruments Incorporated
Charles Fuoco , Texas Instruments Incorporated
Christopher Mobley , Texas Instruments Incorporated
Tim Anderson , Texas Instruments Incorporated
pp. 408

A Scalable High-Performance DMA Architecture for DSP Applications (Abstract)

Dave Comisky , Texas Instruments, Incorporated
Sanjive Agarwala , Texas Instruments, Incorporated
Charles Fuoco , Texas Instruments, Incorporated
pp. 414
Session 6.2: Advanced Architectural Design and Synthesis, Chair: Edward Grochowski, Intel

Efficient Place and Route for Pipeline Reconfigurable Architectures (Abstract)

Seth Copen Goldstein , Carnegie Mellon University
Srihari Cadambi , Carnegie Mellon University
pp. 423

PEAS-III: An ASIP Design Environment (Abstract)

Jun Sato , Tsuruoka National College of Technology
Akichika Shiomi , Shizuoka University
Masaharu Imai , Osaka University
Makiko Itoh , Osaka University
Akira Kitajima , Osaka University
Yoshinori Takeuchi , Osaka University
Shigeaki Higaki , Osaka University
pp. 430

Symbolic Binding for Clustered VLIW ASIPs (Abstract)

Satish Pillai , University of Texas at Austin
Margarida Jacome , University of Texas at Austin
pp. 437

Interfacing Hardware and Software Using C++ Class Libraries (Abstract)

Dinesh Ramanathan , University of California at Irvine
Ray Roth , University of California at Santa Clara
Rajesh Gupta , University of California at Irvine
pp. 445
Session 6.3: Application and Case Studies in Test and Verification, Chair: Carl Pixley, Motorola

Formal Verification of an Industrial System-on-a-Chip (Abstract)

Myung-Kyoon Yim , Samsung Electronics - Korea
Jae-Young Lee , Samsung Electronics - Korea
Yun-Tae Lee , Samsung Electronics - Korea
Hoon Choi , Samsung Electronics - Korea
Byeong-Whee Yun , Samsung Electronics - Korea
pp. 453

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation (Abstract)

Andreas Kuehlmann , IBM T. J. Watson Research Center
Viresh Paruthi , IBM Enterprise Systems Group
pp. 459

Efficient Design Error Correction of Digital Circuits (Abstract)

Thomas Kropf , University of T?bingen
Dirk W. Hoffmann , University of T?bingen
pp. 465

An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design (Abstract)

Alan Troidl , IBM Corporation
Michael Cogswell , IBM Corporation
James Sage , IBM Corporation
Don Pearl , IBM Corporation
pp. 473
Invited Paper

The Birth of the Baby (Abstract)

R.B.E. Napper , University of Manchester
Hilary J. Kahn , University of Manchester
pp. 481
Session 7.1: Logic Optimization, Chair: Chin-Long Wey, Michigan State University

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks (Abstract)

Subarnarekha Sinha , University of California at Berkley
Sunil P. Khatri , University of California at Berkley
Robert K. Brayton , University of California at Berkley
Alberto L. Sangiovanni-Vincentelli , University of California at Berkley
pp. 494

Minimization of Ordered Pseudo Kronecker Decision Diagrams (Abstract)

Per Lindgren , Lule? University of Technology
Rolf Drechsler , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
pp. 504
Session 7.2: High Level Specification and Synthesis, Chair: Pranav Ashar, NEC

Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification (Abstract)

N. Zergainoh , TIMA Laboratory
P. LeMarrec , TIMA Laboratory
P. Coste , TIMA Laboratory
A. Jerraya , TIMA Laboratory
F. Hessel , TIMA Laboratory and Catholic University of Porto Alegre
G. Nicolescu , TIMA Laboratory
pp. 525
Poster Sessions

An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications (Abstract)

Alfredo Benso , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Stefano Martinetto , Politecnico di Torino
Riccardo Mariani , Aurelia Microelettronica
pp. 537

On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs (Abstract)

P. Prinetto , Politecnico di Torino
A. Benso , Politecnico di Torino
F. Ricciato , Politecnico di Torino
S. Chiusano , Politecnico di Torino
M. Spadari , LSI Logic
S. Di Carlo , Politecnico di Torino
M. Lobetti Bodoni , Siemens Information and Communication Networks S.p.A.
pp. 539

Static Timing Analysis with False Paths (Abstract)

Haizhou Chen , Marvell Semiconductor, Inc.
Bing Lu , University of Minnesota
Ding-Zhu Du , University of Minnesota
pp. 541

Cheap Out-of-Order Execution Using Delayed Issue (Abstract)

J.P. Grossman , Massachusetts Institute of Technology
pp. 549

Representing and Scheduling Looping Behavior Symbolically (Abstract)

Steve Haynal , University of California at Santa Barbara
Forrest Brewer , University of California at Santa Barbara
pp. 552

Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond (Abstract)

Satoru Isomura , Hitachi, Ltd.
Kazunobu Nojiri , Hitachi Information Technology Co., Ltd.
Toru Hiyama , Hitachi, Ltd.
Yuko Ito , Hitachi, Ltd.
Eijiro Maeda , Hitachi Information Technology Co., Ltd.
pp. 556

A Register File with Transposed Access Mode (Abstract)

Yongmin Kim , University of Washington
Yoochang Jung , University of Washington
Donglok Kim , University of Washington
Stefan G. Berg , University of Washington
pp. 559

Leakage Power Analysis and Reduction during Behavioral Synthesis (Abstract)

Niraj K. Jha , Princeton University
Kamal S. Khouri , Princeton University
pp. 561

An Advanced Instruction Folding Mechanism for a Stackless Java Processor (Abstract)

Austin Kim , Illinois Institute of Technology
Morris Chang , Illinois Institute of Technology
pp. 565

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet (Abstract)

F. Brglez , North Carolina State University
G. Konduri , Massachusetts Institute of Technology
R. Reese , Mississippi State University
H. Lavana , North Carolina State University
A. Chandrakasan , Massachusetts Institute of Technology
pp. 567

A Decompression Architecture for Low Power Embedded Systems (Abstract)

Haris Lekatsas , Princeton University
Jörg Henkel , NEC USA
Wayne Wolf , Princeton University
pp. 571

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures (Abstract)

N. Bagherzadeh , University of California at Irvine
R. Hermida , Universidad Complutense
R. Maestre , Universidad Complutense
M. Fernandez , Universidad Complutense
F.J. Kurdahi , University of California at Irvine
H. Singh , University of California at Irvine
pp. 575

The M˙CORE(TM) M340 Unified Cache Architecture (Abstract)

Bill Moyer , Motorola, Incorporated
Afzal Malik , Motorola, Incorporated
Dan Cermak , Motorola, Incorporated
pp. 577

Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation (Abstract)

Yao-Wen Chang , National Chiao Tung University
Song-Ra Pan , National Chiao Tung University
pp. 581

Hierarchical Simulation of a Multiprocessor Architecture (Abstract)

Marius Pirvu , Texas A&M University
Laxmi Bhuyan , Texas A&M University
Rabi Mahapatra , Texas A&M University
pp. 585

A Technique for Identifying RTL and Gate-Level Correspondences (Abstract)

Indradeep Ghosh , Fujitsu Labs of America
Srivaths Ravi , Princeton University
Niraj K. Jha , Princeton University
Vamsi Boppana , Fujitsu Labs of America
pp. 591

Source-Level Transformations for Improved Formal Verification (Abstract)

Brian D. Winters , University of British Columbia
Alan J. Hu , University of British Columbia
pp. 599

Author Index (PDF)

pp. 609
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