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2012 IEEE 30th International Conference on Computer Design (ICCD) (2000)
Austin, Texas
Sept. 17, 2000 to Sept. 20, 2000
ISSN: 1063-6404
ISBN: 0-7695-0801-4
pp: 591
Indradeep Ghosh , Fujitsu Labs of America
Srivaths Ravi , Princeton University
Niraj K. Jha , Princeton University
Vamsi Boppana , Fujitsu Labs of America
ABSTRACT
In this paper, we consider the mapping problem of identifying correspondences between a signal in a high-level specification and a net in a lower-level implementation for a given design. Conventional techniques use shared names to associate a signal with a net whenever possible. However, given that a synthesis flow may not preserve names, solutions to the above problem eventually take recourse to expensive alternatives such as formal verification. This work provides a robust framework for identifying RTL signal to gate-level net correspondences for a given design. Our technique exploits the observation that circuit diagnosis provides a convenient means for locating faults in a gate-level network. Since our problem requires locating gate-level nets corresponding to RTL signals, we formulate the mapping problem as a query whose solution is provided by a circuit diagnosis engine. Our experimental work with industrial designs for many mapping cases shows that our solution to the mapping problem is (i) fast, and (ii) precise in identifying the gate-level equivalents (the number of nets returned by our mapping engine for a query is typically 1 or 2 even for designs with tens of thousands of VHDL lines).
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CITATION
Indradeep Ghosh, Srivaths Ravi, Niraj K. Jha, Vamsi Boppana, "A Technique for Identifying RTL and Gate-Level Correspondences", 2012 IEEE 30th International Conference on Computer Design (ICCD), vol. 00, no. , pp. 591, 2000, doi:10.1109/ICCD.2000.878351
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