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2012 IEEE 30th International Conference on Computer Design (ICCD) (1999)
Austin, Texas
Oct. 10, 1999 to Oct. 13, 1999
ISSN: 1063-6404
ISBN: 0-7695-0406-X
TABLE OF CONTENTS

Foreword (PDF)

pp. xvi

Reviewers (PDF)

pp. xxii
Session 1.1.1: Keynote Address

System Design: Traditional Concepts and New Paradigms (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Alberto Ferrari , University of California at Berkeley
pp. 2

The MARCO/DARPA Gigascale Silicon Research Center (Abstract)

Kurt. Keutzer , University of California at Berkeley
A. Richard Newton , University of California at Berkeley
pp. 14
Session 1.3.1: Embedded Tutorial
Session 1.3.2: Applied Verification Techniques, Co-Chairs: Carl Pixley, Motorola, USA and Warren Hunt, IBM Austin Research Laboratory, USA

Formal Verification of Synthesized Analog Designs (Abstract)

Abhijit Ghosh , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 40

Automatic Error Correction of Tri-State Circuits (Abstract)

Dirk W. Hoffmann , University of Tuebingen
Thomas Kropf , University of Tuebingen
pp. 51
Session 1.3.3: Computer Arithmetic, Chair: Kevin Nowka, IBM Austin Research Laboratory, USA

Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder (Abstract)

Sumio Morioka , IBM Research, Tokyo Research Laboratory
Yasunao Katayama , IBM Research, Tokyo Research Laboratory
pp. 60

High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection (Abstract)

Earl E. Swartzlander, Jr. , University of Texas at Austin
Jae-Hyuck Kwak , University of Texas at Austin
Jae hun Choi , University of Texas at Austin
pp. 68

Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition (Abstract)

Javier D. Bruguera , University of Santiago de Compostela
Tomas Lang , University of California at Irvine
pp. 73
Lunch Presentation
Session 1.4.1: Machines and Characterization, Chair: Chris Newburn, Intel, USA

Designing the M?CORE™ M3 CPU Architecture (Abstract)

Lea Hwang Lee , Motorola Incorporated
Jeff Scott , Motorola Incorporated
Bill Moyer , Motorola Incorporated
John Arends , Motorola Incorporated
Ann Chin , Motorola Incorporated
pp. 94

Performance Evaluation of Configurable Hardware Features on the AMD-K5 (Abstract)

Mike Clark , University of Texas at Austin
Lizy Kurian John , University of Texas at Austin
pp. 102

Detailed Characterization of a Quad Pentium Pro Server Running TPC-D (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign
Bob Knighten , Intel Corporation
Josep Lluis Larriba-Pey , Universitat Politecnica de Catalunya
Pedro Trancoso , Intercollege Limassol
Youjip Won , Intel Corporation
Qiang Cao , University of Illinois at Urbana-Champaign
pp. 108
Session 1.4.2: Power and Noise Considerations in Microprocessor Design, Chair: Priyadarsan Patra, Intel, USA
Session 1.4.3: Architectures for Embedded Systems, Chair: Tom Truman, Lucent Bell Laboratories, USA

A DSP with Caches—A Study of the GSM-EFR Codec on the TI C6211 (Abstract)

Tor Jeremiassen , Bell Laboratories - Lucent Technologies
pp. 138

Evaluation of Computing in Memory Architectures for Digital Image Processing Applications (Abstract)

David Landis , Pennsylvania State University
Paul Hulina , Pennsylvania State University
Lee Coraor , Pennsylvania State University
Luke Roth , Pennsylvania State University
Scott Deno , Pennsylvania State University
pp. 146
Session 1.4.4: Built-In Self Test, Chair: Cheng-Ping Wang, Texas Instruments, USA
Session 1.5.1: Intelligent Memory, Chair: Doug Burger, The University of Texas at Austin, USA

FlexRAM: Toward an Advanced Intelligent Memory System (Abstract)

Vinh Lam , University of Illinois at Urbana Champaign
Diana Keen , University of Illinois at Urbana Champaign
Zhenzhou Ge , University of Illinois at Urbana Champaign
Wei Huang , University of Illinois at Urbana Champaign
Josep Torrellas , University of Illinois at Urbana Champaign
Yi Kang , University of Illinois at Urbana Champaign
Seung-Moon Yoo , University of Illinois at Urbana Champaign
pp. 192
Session 1.5.2: Performance and Area Optimization, Chair: Shantanu Ganguly, Intel, USA

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation (Abstract)

D.F. Wong , University of Texas at Austin
Hai Zhou , Synopsys Incorporated
I-Min Liu , University of Texas at Austin
Adnan Aziz , University of Texas at Austin
pp. 210

An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs (Abstract)

K.K. Lee , University of Texas at Austin
D.F. Wong , University of Texas at Austin
pp. 216
Session 1.5.3: VLSI Implementation of Arithmetic Circuits, Chair: Magdy Abidir, Motorola, USA

Low-Power Radix-4 Combined Division and Square Root (Abstract)

Tomas Lang , University of California at Irvine
Alberto Nannarelli , University of California at Irvine
pp. 236

A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders (Abstract)

Bong-Il Park , Korea Advanced Institute of Science and Technology
In-Cheol Park , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
pp. 243
Session 1.5.4: Design Convergence, Chair: Georg Pelz, Gerhard-Mercator University GH, Duisberg, Germany

A Robust Solution to the Timing Convergence Problem in High-Performance Design (Abstract)

Hi-Keung Ma , Synopsys Incorporated
Robert Damiano , Synopsys Incorporated
Paul Thilking , 3DFX International
Narendra Shenoy , Synopsys Incorporated
Kevin Harer , Synopsys Incorporated
Mahesh Iyer , Synopsys Incorporated
pp. 250

Performance Driven Optimization of Network Length in Physical Placement (Abstract)

Prabhakar Kudva , IBM T.J Watson Research Center
Wilm Donath , IBM T.J Watson Research Center
Lakshmi Reddy , IBM Server Division
pp. 258

Efficient Crosstalk Estimation (Abstract)

Martin Kuhlmann , University of Minnesota
Keshab K. Parhi , University of Minnesota
Sachin S. Sapatnekar , University of Minnesota
pp. 266
Session 1.6: Poster Presentations

A High-Performance Hardware-Efficient Memory Allocation Technique and Design (Abstract)

Sadiq M. Sait , King Fahd University of Petroleum and Minerals
Hasan Cam , King Fahd University of Petroleum and Minerals
Mostafa Abd-El-Barr , King Fahd University of Petroleum and Minerals
pp. 274

A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing (Abstract)

Makoto Hanawa , Hitachi Limited
Eiki Kamada , Hitachi Limited
Tatsuya Kawashimo , Hitachi Limited
Kentaro Shimada , Hitachi Limited
Ryo Yamagata , Hitachi Limited
pp. 279

Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels (Abstract)

Ramesh Radhakrishnan , University of Texas at Austin
Juan Rubio , University of Texas at Austin
Lizy Kurian John , University of Texas at Austin
pp. 281

Automatic Generation of Tree Multipliers Using Placement-Driven Netlists (Abstract)

Avinash K. Gautam , Texas Instruments India Limited
S.K. Nandy , Indian Institute of Science
V. Visvanathan , Indian Institute of Science
pp. 285

Yield Optimization by Design Centering and Worst-Case Distance Analysis (Abstract)

G.S Samudra , National University of Singapore
H.M. Chen , National University of Singapore
D.S.H. Chan , National University of Singapore
Yaacob Ibrahim , National University of Singapore
pp. 289

Area, Performance, and Yield Implications of Redundancy in On-Chip Caches (Abstract)

Tom Thomas , Motorola Incorporated
Brian Anthony , Motorola Incorporated
pp. 291

CalmRISC™: A Low Power Microcontroller with Efficient Coprocessor Interface (Abstract)

Seh-Woong Jeong , Samsung Electronics Co. and KAIST
Hong-Kyu Kim , Samsung Electronics Co. and KAIST
Kyoung-Mook Lim , Samsung Electronics Co. and KAIST
Hyung-Lae Roh , Samsung Electronics Co. and KAIST
Seung-Jae Jeong , Samsung Electronics Co. and KAIST
H.S. Yang , Samsung Electronics Co. and KAIST
Yang-Ho Kim , Samsung Electronics Co. and KAIST
Bong-Young Chung , Samsung Electronics Co. and KAIST
Yong-Chun Kim , Samsung Electronics Co. and KAIST
pp. 299

An Even Wiring Approach to the Ball Grid Array Package Routing (Abstract)

Shuenn-Shi Chen , National Taiwan University
Jong-Jang Chen , National Taiwan University
Chia-Chun Tsai , National Taipei University of Technology
Sao-Jie Chen , National Taiwan University
pp. 303

Synthesis of Pseudo Kronecker Lattice Diagrams (Abstract)

Per Lindgren , Lule University of Technology
Bernd Becker , Albert-Ludwigs-University
Rolf Drechsler , Albert-Ludwigs-University
pp. 307

Generic Universal Switch Blocks (Abstract)

Yu-Dong Chang , National Chiao Tung University
Guang-Ming Wu , National Chiao Tung University
Yao-Wen Chang , National Chiao Tung University
Michael Shyu , National Chiao Tung University
pp. 311

Multi-Level Logic Minimization through Fault Dictionary Analysis (Abstract)

M. Ray Mercer , Texas A&M University
Ronald W. Mehler , University of Texas at Dallas
pp. 315

A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping (Abstract)

Seong Yong Ohm , Seoul Women's University
Kang Yi , Handong University
pp. 319

Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis (Abstract)

Ashok Kumar , University of Southwestern Louisiana
Magdy Bayoumi , University of Southwestern Louisiana
pp. 321

An Efficient Functional Coverage Test for HDL Descriptions at RTL (Abstract)

Chien-Nan Jimmy Liu , National Chiao Tung University
Jing-Yang Jou , National Chiao Tung University
pp. 325

An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment (Abstract)

Hyunjin Kim , Yonsei University
Sungho Kang , Yonsei University
Jongchul Shin , Yonsei University
pp. 328

On-Line BIST for Testing Analog Circuits (Abstract)

I. Rayane , TIMA/INPG
M. Nicolaidis , TIMA/INPG
J. Velasco-Medina , TIMA/INPG
pp. 330
Session 1.7: Panel Discussion
Session 2.1: Plenary
Session 2.2.1: System Level Issues, Chair: Margarida Jacome, The University of Texas at Austin, USA

A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology (Abstract)

Vilesh Shah , Texas Instruments India Ltd
Subash Chandar , Texas Instruments India Ltd
Amitabh Menon , Texas Instruments India Ltd
Jagadish Rao , Texas Instruments India Ltd
Avinask K. Gautam , Texas Instruments India Ltd
H Udayakumar , Texas Instruments India Ltd
Karthikeyan Madathil , Texas Instruments India Ltd
pp. 340

Architectural Synthesis of Timed Asynchronous Systems (Abstract)

Chris J. Myers , University of Utah
Hao Zheng , University of Utah
Brandon M. Bachman , Hewlett-Packard Company
pp. 354

Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD (Abstract)

Jing-Yang Jou , National Chiao Tung University
Hen-Ming Lin , National Chiao Tung University
pp. 364
Session 2.2.2: Compilers and Algorithms, Chair: Steve Keckler, The University of Texas at Austin, USA

A Compiler-Assisted Data Prefetch Controller (Abstract)

David J. Lilja , University of Minnesota
Steven P. VanderWiel , University of Minnesota
pp. 372

Energy and Performance Improvements in Microprocessor Design Using a Loop Cache (Abstract)

Nikolaos Bellas , University of Illinois at Urbana-Champaign
George Stamoulis , University of Illinois at Urbana-Champaign
Constantine Polychronopoulos , University of Illinois at Urbana-Champaign
Ibrahim Hajj , University of Illinois at Urbana-Champaign
pp. 378

A Fast Median Filter Using AltiVec (Abstract)

Wen Su , Motorola, Incorporated
Priyadarshan Kolte , Motorola, Incorporated
Roger Smith , Motorola, Incorporated
pp. 384

Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees (Abstract)

Guoliang Xue , University of Vermont
Guo-Hui Lin , University of Vermont
Defang Zhou , University of Vermont
pp. 392
Session 2.2.3: Test Generation and Delay Testing, Chair: Karim Arabi, Ecole de Technologie Superieure (ETS), Canada

On Detecting Bridges Causing Timing Failures (Abstract)

Sandip Kundu , Intel Corporation
Sreenivas Mandava , Intel Corporation
Sreejit Chakravarty , Intel Corporation
pp. 400

Design for Testability to Combat Delay Faults (Abstract)

Jacob Savir , New Jersey Institute of Technology
pp. 407

Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip (Abstract)

Nur A. Touba , University of Texas at Austin
Abhijit Jas , University of Texas at Austin
pp. 418
Session 2.3.1: Microarchitecture, Chair: Andrew Pleszkun, University of Colorado, USA

Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications (Abstract)

D. Scott Wills , Georgia Institute of Technology
Lucian Codrescu , Georgia Institute of Technology
pp. 428

Load-Balancing Branch Target Cache and Prefetch Buffer (Abstract)

Jun-Li Yuan , National University of Singapore
Chi-Hung Chi , National University of Singapore
pp. 436

Dynamic Branch Decoupled Architecture (Abstract)

Hon-Chi Ng , Iowa State University
Akhilesh Tyagi , Iowa State University
Prasant Mohapatra , Michigan State University
pp. 442
Session 2.3.2: Efficient State-Space Exploration, Chair: Anna Slobodova, Compaq, USA

Improving Witness Search Using Orders on States (Abstract)

Jayanta Bhadra , University of Texas At Austin
Jacob Abraham , University of Texas At Austin
Rob Sumners , University of Texas At Austin
pp. 452

Efficient Fixpoint Computation for Invariant Checking (Abstract)

Fabio Somenzi , University of Colorado at Boulder
Kavita Ravi , Cadence Design Systems
pp. 467
Session 2.3.3: Clocking and Analog Circuit Prototyping, Chair: Rajesh Galivanche, Intel, USA

Transmission Line Clock Driver (Abstract)

Matthew E. Becker , Massachusetts Institute of Technology
Thomas F. Knight, Jr. , Massachusetts Institute of Technology
pp. 489
Session 2.3.4: Embedded Tutorial, Organizer and Chair: Andreas Both, Motorola Semiconductor Products Sector, USA

Benchmarking, Selection and Debugging of Microcontrollers (Abstract)

Alan R. Weiss , EEA4BC Certification Laboratories, LLC
pp. 492

A New Development Tool with the IEEE-ISTO (Abstract)

Ronald Stence , Motorola Corporation
pp. 499

32-Bit Architectures for Embedded Systems (Abstract)

Ronald Stence , Motorola Corporation
pp. 503
Invited Session 2.4.1: Digital Signal Processors, Organizer and Chair: Ken Shepard, Columbia University, USA

DSP for the Third Generation Wireless Communications (Abstract)

Edgar Auslander , Texas Instruments Incorporated
Mike McMahan , Texas Instruments Incorporated
Uming Ko , Texas Instruments Incorporated
pp. 516

Performance and Reliability Verification of C6201/C6701 Digital Signal Processors (Abstract)

Sudha Thiruvengadam , Texas Instruments Incorporation
Frank Cano , Texas Instruments Incorporation
Deepak Kapoor , Texas Instruments Incorporation
Nagaraj Ns , Texas Instruments Incorporation
pp. 521
Session 2.4.2: Caching Approaches, Chair: Mauricio Breternitz, Motorola, USA

Pursuing the Performance Potential of Dynamic Cache Line Sizes (Abstract)

Peter van Vleet , University of Washington
Anna Karlin , University of Washington
Lindsay Brown , University of Washington
Eric Anderson , University of Washington
Jean-Loup Baer , University of Washington
pp. 528

Cache Optimization for Memory-Resident Decision Support Commercial Workloads (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign
Pedro Trancoso , Intercollege Limassol
pp. 546
Session 2.4.3: CMOS Circuit Design Techniques, Chair: Sharad Mehrotra, IBM, USA

An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits (Abstract)

Sarma Vrudhula , University of Arizona
Qi Wang , Cadence Design Systems
pp. 556

Design and Synthesis of Monotonic Circuits (Abstract)

Tyler Thorp , University of Washington
Carl Sechen , University of Washington
Gin Yee , University of Washington
pp. 569

SOI Implementation of a 64-Bit Adder (Abstract)

J.V. Tran , IBM Corporation
D.L. Stasiak , IBM Corporation
S.N. Storino , IBM Corporation
F. Mounes-Toussi , IBM Corporation
pp. 573
Session 3.1: Plenary
Invited Session 3.2.1

TriMedia CPU64 Application Domain and Benchmark Suite (Abstract)

A.K. Riemens , Philips Research Labs
R.J. Schutten , Philips Research Labs
F.W. Sijstermans , Philips Semiconductors TriMedia
G.J. Hekstra , Philips Research Labs
G.D. La Hei , Philips Research Labs
K.A. Vissers , Philips Research Labs
pp. 580

TriMedia CPU64 Architecture (Abstract)

F.W. Sijstermans , Philips Semiconductors
A.D. Pimentel , University of Amsterdam
P. Struik , Philips Research Laboratories Eindhoven
H.P.E. Vranken , Philips Research Laboratories Eindhoven
E.J.D. Pol , Philips Research Laboratories Eindhoven
M.J.A. Tromp , Philips Semiconductors
P. van der Wolf , Philips Research Laboratories Eindhoven
J.T.J. Van Eijndhoven , Philips Research Laboratories Eindhoven
K.A. Vissers , Philips Research Laboratories Eindhoven
R.H.J. Bloks , Philips Research Laboratories Eindhoven
pp. 586

TriMedia CPU64 Application Development Environment (Abstract)

E.J.D. Pol , Philips Research Laboratories Eindhoven
M.J.A. Tromp , Philips Semiconductors
F.W. Sijstermans , Philips Semiconductors
B.J.M. Aarts , Philips Research Laboratories Eindhoven
P. Struik , Philips Research Laboratories Eindhoven
J.T.J. Van Eindhoven , Philips Research Laboratories Eindhoven
P. van der Wolf , Philips Research Laboratories Eindhoven
J.W. van de Waerdt , Philips Semiconductors
pp. 593

TriMedia CPU64 Design Space Exploration (Abstract)

G.D. La Hei , Philips Research Labs, Eindhoven
G.J. Hekstra , Philips Research Labs, Eindhoven
F.W. Sijstermans , Philips Semiconductors
P. Bingley , Philips Research Labs, Eindhoven
pp. 599
Session 3.2.2: Logic Synthesis, Chair: Ken Shepard, Columbia University, USA

Synthesis of Arrays and Records (Abstract)

Rudra Mukherjee , ViewLogic Systems Incorporated
Steven Barnfield , IBM EDA Lab
Pradip K. Jha , IBM EDA Lab
Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center
John Weaver , IBM EDA Lab
pp. 614

Decomposition of Finite State Machines for Area, Delay Minimization (Abstract)

H. Narayanan , Indian Institute of Technology at Bombay.
Rupesh S. Shelar , Silicon Automation Systems Limited
Madhav P. Desai , Indian Institute of Technology at Bombay.
pp. 620

BDD Decomposition for Efficient Logic Synthesis (Abstract)

Vigyan Singhal , Cadence Berkeley Laboratory
Maciej Ciesielski , University of Massachusetts at Amherst
Congguang Yang , University of Massachusetts at Amherst
pp. 626
Session 3.2.3: Hardware Software Partitioning and Synthesis, Chair: Miodrag Potkonjak, University of California at Los Angeles, USA

Software Synthesis for Complex Reactive Embedded Systems (Abstract)

Massimiliano Chiodo , Cadence Berkeley Labs Cadence Design Systems
Felice Balarin , Cadence Berkeley Labs Cadence Design Systems
pp. 634

Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory (Abstract)

Romain Kamdem , Universit? de Provence
Alain Fonkoua , Ecole Sup?rieure d'Ingenieur de Marseille
Andre Zenatti , CNRS-IBSM-IFR1
pp. 640

Compositional Software Synthesis of Communicating Processes (Abstract)

Bill Lin , University of California at San Diego
Xiaohan Zhu , University of California at San Diego
pp. 646

Preference-Driven Hierarchical Hardware/Software Partitioning (Abstract)

Sharon (Xiaobo) Hu , University of Notre Dame
Gang Quan , University of Notre Dame
Garrison Greenwood , Western Michigan University
pp. 652

Author Index (PDF)

pp. 658
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