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2012 IEEE 30th International Conference on Computer Design (ICCD) (1999)
Austin, Texas
Oct. 10, 1999 to Oct. 13, 1999
ISSN: 1063-6404
ISBN: 0-7695-0406-X
pp: 340
Vilesh Shah , Texas Instruments India Ltd
Subash Chandar , Texas Instruments India Ltd
Amitabh Menon , Texas Instruments India Ltd
Jagadish Rao , Texas Instruments India Ltd
Avinask K. Gautam , Texas Instruments India Ltd
H Udayakumar , Texas Instruments India Ltd
Karthikeyan Madathil , Texas Instruments India Ltd
We present a design methodology that was used to design a 150MHz DSP core in a deep sub-micron technology, with emphasis on high speed and fast design cycle time. We detail the methodology, primarily based on synthesis, describe how we coupled synthesis to placement and layout and present data on our timing convergence results. We present data on experiments that we performed to tune specific steps of the methodology, which were critical to make the methodology successful.
Design Methodology, Synthesis, Links to layout, Deep sub-micron, Physical Design, DSP
Vilesh Shah, Subash Chandar, Amitabh Menon, Jagadish Rao, Avinask K. Gautam, H Udayakumar, Karthikeyan Madathil, "A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology", 2012 IEEE 30th International Conference on Computer Design (ICCD), vol. 00, no. , pp. 340, 1999, doi:10.1109/ICCD.1999.808564
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