Welcome to ICCD '98 (PDF)

Program Committee (PDF)

Reviewers (PDF)

Deep Blue: The IBM Chess Machine (PDF)

Making Computer-Dependent Airplanes Safer through Formal Methods (PDF)

A 690ps Read-Access Latency Register File for a GHz Integer Microprocessor (Abstract)

Circuit Design Techniques for a Gigahertz Integer Microprocessor (Abstract)

Design Methodology for a 1.0 GHz Microprocessor (Abstract)

Improved Built-In Test Pattern Generators Based on Comparison Units for Synchronous Sequential Circuits (Abstract)

Efficient BIST TPG Design and Test Set Compaction for Delay Testing via Input Reduction (Abstract)

Testing Digital to Analog Converters based on Oscillation-Test Strategy using Sigma-delta Modulation (Abstract)

System-Level Performance Estimation Strategy for Sw and Hw (Abstract)

Accuracy Sensitive Word--Length Selection for Algorithm Optimization (Abstract)

Optimal design of synchronous circuits using software pipelining techniques (Abstract)

On Short Circuit Power Estimation of CMOS Inverters (Abstract)

Methods for Calculating Coupling Noise in Early Design: A Comparative Analysis (Abstract)

Low Power SRAM Design using Hierarchical Divided Bit-Line Approach (Abstract)

The Transformation of the IBM S/390 Enterprise Servers (PDF)

The Alpha 21264 Microprocessor Architecture (Abstract)

Timing Verification of the 21264: A 600MHz Full-Custom Microprocessor (Abstract)

Circuit Implementation of a 600MHz Superscalar RISC Microprocessor (Abstract)

Zen and the Art of Alpha Verification (Abstract)

Technology Challenges for Design and Computer-Aided Design of Digital Integrated Circuits (PDF)

A Reduction Scheme to Optimize the Wallace Multiplier (Abstract)

Fast Low-Power Shared Division and Square-Root Architecture (Abstract)

Area Minimization of Redundant CORDIC Pipeline Architectures (Abstract)

How Many Logic Levels Does Floating-Point Addition Require? (Abstract)

Efficient Exact and Heuristic Minimization of Hazard-Free Logic (Abstract)

Area-Oriented Synthesis for Pass-Transistor Logic (Abstract)

New Compact Representation of Multiple-Valued Functions, Relations, and Non-deterministic State Machines (Abstract)

A Low-Power Logic Optimization Methodology based on a Fast Power-Driven Mapping (Abstract)

A Fine-Grain, Current Mode Scheme for VLSI Proximity Search Engine (Abstract)

An Effective Datapath Design Methodology for High-Frequency Design (Abstract)

Adaptive Synchronization (Abstract)

The Microcore Development System ? A Unified Environment for Designing New Microprocessors (Abstract)

Automatic Data Path Abstraction for Verification of Large Scale Designs (Abstract)

Model Checking of a Real ATM Switch (Abstract)

Performance-Driven Board-Level Routing for FPGA-based Logic Emulation (Abstract)

Re-synthesis in Technology Mapping for Heterogeneous FPGAs (Abstract)

A Simple Adaptive Wormhole Routing Algorithm for MIMD Systems (Abstract)

Branch Assertion and Elimination (Abstract)

High-Performance Digit-Serial Complex-Number Multiplier-Accumulator (Abstract)

Dynamic Fault Diagnosis for Sequential Circuits on Reconfigurable Hardware (Abstract)

On Thin Boolean Functions and Related Optimal OBDD Ordering (Abstract)

Clock-Skew Constrained Placement for Row Based Designs (Abstract)

Antirandom vs. Psuedorandom Testing (Abstract)

Formal Verification ¾ "Peripheral" or "Indispensable"? (PDF)

Architects Should not Write Checks that Design Teams Can't Cash (PDF)

The ARM9 Family - High Performance Microprocessors for Embedded Applications (Abstract)

The System Design of a Windows CE ARM based Micro-controller (Abstract)

Hardware/Software Co-verification, an IP Vendors Viewpoint (Abstract)

AMULET3: A High-Performance Self-Timed ARM Microprocessor (Abstract)

Dynamically and Partially Reconfigurable Architectures: New Opportunities and Challenges (PDF)

Noise and Signal Integrity Issues in Deep Submicron Design (PDF)

Deep Submicron Design Techniques for the 500MHz IBM S/390 G5 Custom Microprocessor (Abstract)

Comparative Analysis of Latches and Flip-Flops for High-Performance Systems (Abstract)

Design Issues in Mixed Static-Domino Circuit Implementations (Abstract)

A Fast Global Gate Collapsing Technique for High Performance Designs using Static CMOS and Pass Transistor Logic (Abstract)

AltiVec: Motorola's High Performance Vector Parallel Processing Expansion to the PowerPC Architecture (PDF)

A Minimized Hardware Architecture of Fast Phong Shader Using Taylor Series Approximation in 3D Graphics (Abstract)

Pipelined Computation of LNS Addition/Subtraction with Very Small Lookup Tables (Abstract)

Leading-One Prediction Scheme for Latency Improvement in Single Datapath Floating--Point Adders (Abstract)

An Approach to Verify a Large Scale System-on-a-chip Using Symbolic Model Checking (Abstract)

To Model Check Or Not To Model Check (Abstract)

VEGA: A Verification Tool Based on Genetic Algorithms (Abstract)

Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors (Abstract)

FPGA-Based Internet Protocol Version 6 Router (Abstract)

Partitioning in Time : A Paradigm for Reconfigurable Computing (Abstract)

Pulse-Mode Macromodular Systems (Abstract)

Practical Design and Performance Evaluation of Completion Detection Circuits (Abstract)

Rapid Prototyping of Self-timed Circuits (Abstract)

Evaluating the Performance of Active Cache Management Schemes (Abstract)

Data Cache Parameter Measurements (Abstract)

Fault-Tolerant Architecture for High Performance Embedded System Applications (Abstract)

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis (Abstract)

Incorporating Timing Constraints in the Efficient Memory Model for Symbolic Ternary Simulation (Abstract)

Timing Analysis of Combinational Circuits Containing Complex Gates (Abstract)

Extension of the Working-Zone-Encoding Method to Reduce the Energy on the Microprocessor Data Bus (Abstract)

Low-Power Radix-8 Divider (Abstract)

A Self-Timed Real-Time Sorting Network (Abstract)

Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement (Abstract)

DCP: an Algorithm for Datapath/Control Partitioning of Synthesizable RTL Models (Abstract)

Hierarchical Pipelining for Behaviors, Loops and Operations (Abstract)

Legacy Instruction Sets: Aging Like Fine Wine, or Rusting Like Old Buicks? (PDF)

Venture Capital and the Start-up Company (PDF)

The Unbundling of the Semiconductor Industry (PDF)

Silicon Microsystems ? Merging Sensors, Circuits and Systems (Abstract)

Circular Buffered Switch Design with Wormhole Routing and Virtual Channels (Abstract)

The Effects of Explicitly Parallel Mechanisms on the Multi-ALU Processor Cluster Pipeline (Abstract)

Parallel Ultra Large Scale Engine SIMD Architecture For Real-Time Digital Signal Processing Applications (Abstract)

An Eight Issue Tree-VLIW Processor for Dynamic Binary Translation (Abstract)

On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits (Abstract)

Enhancing Topological ATPG with High-Level Information and Symbolic Techniques (Abstract)

An Exact Solution to the Minimum Size Test Pattern Problem (Abstract)

Using Regression Analysis for GA-Based ATPG Parameter Optimization (Abstract)

Static Race Verification for Networks with Reconvergent Clocks (Abstract)

Finding The Longest Simple Path in Cyclic Combinational Circuits (Abstract)

Practical Use of Transition Mode Delay to Solve the Problems of Floating Mode Delay under Highly Correlated Input Streams (Abstract)

A Fractal Compaction Algorithm for Efficient Power Estimation (Abstract)

Code Coalescing Unit: A Mechanism to Facilitate Load Store Data Communication (Abstract)

Profiling for Input Predictable Threads (Abstract)

Analysis of x86 Instruction Set Usage for DOS/Windows Applications and Its Implication on Superscalar Design (Abstract)

Current-Based Testing for Analog and Mixed-Signal Circuits (Abstract)

Test Points Selection Process and Diagnosability Analysis of Analog Integrated Circuits (Abstract)

Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives (Abstract)

Buffer Size Driven Partitioning for HW/SW Co-Design (PDF)

Scheduling Under Data and Control Dependencies for Heterogeneous Architectures (Abstract)

Integrated Partitioning and Scheduling for Hardware/Software Co-design (Abstract)

Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization (Abstract)

Learning as Applied to Stochastic Optimization for Standard Cell Placement (Abstract)

Timing-Driven Routing for Symmetrical-Array-Based FPGAs (Abstract)

Author Index (PDF)