The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (1998)
Austin, Texas
Oct. 5, 1998 to Oct. 5, 1998
ISSN: 1063-6404
ISBN: 0-8186-9099-2

Program Committee (PDF)

pp. xvii

Reviewers (PDF)

pp. xix
Session 1.1: Keynote Speech
Session 1.2: Plenary
Special Invited Session 1.3.1: A Prototype 1 GHz PowerPC Microprocessor

Circuit Design Techniques for a Gigahertz Integer Microprocessor (Abstract)

Kevin J. Nowka , IBM Austin Research Laboratory
Tibi Galambos , IBM Haifa Research Laboratory
pp. 11
Session 1.3.2: Built-in-Self-Test
Session 1.3.3: Design Optimization

System-Level Performance Estimation Strategy for Sw and Hw (Abstract)

William Fornaciari , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
Fabio Salice , Politecnico di Milano
Alberto Allara , ITALTEL
pp. 48

Accuracy Sensitive Word--Length Selection for Algorithm Optimization (Abstract)

Alice C. Parker , University of Southern California
Suhrid A. Wadekar , University of Southern California
pp. 54

Optimal design of synchronous circuits using software pipelining techniques (Abstract)

El Mostapha Aboulhamid , Universit? de Montr?al
I.E. Bennour 3 , Northern Telecom
François-R. Boyer , Universit? de Montr?al
Y. Savaria , ?cole Polytechnique de Montr?al
pp. 62
Session 1.3.4: Power and Noise Estimation and Optimization

On Short Circuit Power Estimation of CMOS Inverters (Abstract)

Qi Wang , The University of Arizona
Sarma B.K. Vrudhula , The University of Arizona
pp. 70
Lunch Presentation
Special Invited Session 1.4.1: The Alpha 21264 Microprocessor

Timing Verification of the 21264: A 600MHz Full-Custom Microprocessor (Abstract)

Nadir Rahman , Compaq Computer Corporation
Jim Farrell , Compaq Computer Corporation
Emily Shriver , Compaq Computer Corporation
Nevine Nassif , Compaq Computer Corporation
Dale Hall , Compaq Computer Corporation
Nick Rethman , Compaq Computer Corporation
Gill Watt , Compaq Computer Corporation
pp. 96
Session 1.4.2: Technical Forum
Session 1.4.3: Arithmetic I

A Reduction Scheme to Optimize the Wallace Multiplier (Abstract)

Earl Swartzlander, Jr. , University of Texas at Austin
Moises E. Robinson , University of Texas at Austin
pp. 122

Fast Low-Power Shared Division and Square-Root Architecture (Abstract)

Martin Kuhlmann , University of Minnesota
Keshab K. Parhi , University of Minnesota
pp. 128

How Many Logic Levels Does Floating-Point Addition Require? (Abstract)

Peter-Michael Seidel , University of Saarland
Guy Even , Tel-Aviv University
pp. 142
Session 1.4.4: Logic Synthesis

Efficient Exact and Heuristic Minimization of Hazard-Free Logic (Abstract)

J.W.J.M. Rutten , Eindhoven University of Technology
M.R.C.M. Berkelaar , Eindhoven University of Technology
pp. 152

A Low-Power Logic Optimization Methodology based on a Fast Power-Driven Mapping (Abstract)

Sumit Roy , Ambit Design Systems
Harm Arts , Ambit Design Systems
Prithviraj Banerjee , Northwestern University
pp. 175
Poster Session 1.5

Adaptive Synchronization (Abstract)

Rakefet Kol , Technion-Israel Institute of Technology
Ran Ginosar , Technion-Israel Institute of Technology
pp. 188

Automatic Data Path Abstraction for Verification of Large Scale Designs (Abstract)

Viresh Paruthi , University of Cincinnati
Ranga Vemuri , University of Cincinnati
Nazanin Mansouri , University of Cincinnati
pp. 192

Model Checking of a Real ATM Switch (Abstract)

Jianping Lu , Concordia University
Sofiene Tahar , Concordia University
Dan Voicu , University of Montreal
Xiaoyu Song , University of Montreal
pp. 195

Performance-Driven Board-Level Routing for FPGA-based Logic Emulation (Abstract)

Wai-Kei Mak , University of Texas at Austin
D.F. Wong , University of Texas at Austin
pp. 199

Re-synthesis in Technology Mapping for Heterogeneous FPGAs (Abstract)

Jonathan Saul , Oxford University
Maurice Inuani , Oxford University
pp. 202

A Simple Adaptive Wormhole Routing Algorithm for MIMD Systems (Abstract)

Raju D. Venkataramana , Univ of South Florida
N. Ranganathan , Univ of Texas at El Paso
pp. 205

Branch Assertion and Elimination (Abstract)

Afshin Ganjoo , University of Southwestern Louisiana
pp. 208

High-Performance Digit-Serial Complex-Number Multiplier-Accumulator (Abstract)

Keshab K. Parhi , University of Minnesota
Yun-Nan Chang , University of Minnesota
pp. 211

Antirandom vs. Psuedorandom Testing (Abstract)

Yashwant K. Malaiya , Colorado State University
ShenHui Wu , Colorado State University
Anura P. Jayasumana , Colorado State University
pp. 221
Session 1.6.1: Panel
Session 2.1: Plenary
Special Invited Session 2.2.1: The ARM Microprocessor

AMULET3: A High-Performance Self-Timed ARM Microprocessor (Abstract)

S.B. Furber , The University of Manchester,
D.A. Gilbert , Cogency Technology, Inc.,
J. D. Garside , The University of Manchester,
pp. 247
Session 2.2.2: Technical Forum
Embedded Tutorial
Session 2.2.4: High Performance Design Techniques

Comparative Analysis of Latches and Flip-Flops for High-Performance Systems (Abstract)

Raminder Bajwa , Hitachi America Ltd
Vladimir Stojanovic , University of Belgrade
Vojin Oklobdzija , Integration, Berkeley, CA
pp. 264
Lunch Presentation
Session 2.3.1: Arithmetic II

A Minimized Hardware Architecture of Fast Phong Shader Using Taylor Series Approximation in 3D Graphics (Abstract)

Hyun-Chul Shin , Korea Advanced Institute of Science and Technology
Jin-Aeon Lee , Korea Advanced Institute of Science and Technology
Lee-Sup Kim , Korea Advanced Institute of Science and Technology
pp. 286

Leading-One Prediction Scheme for Latency Improvement in Single Datapath Floating--Point Adders (Abstract)

Tomas Lang , University of California at Irvine
Javier D. Bruguera , University of Santiago de Compostela
pp. 298
Session 2.3.2: Practical Functional Verification

To Model Check Or Not To Model Check (Abstract)

Jacob Abraham , University of Texas at Austin
Nina Saxena , University of Texas at Austin
pp. 314

VEGA: A Verification Tool Based on Genetic Algorithms (Abstract)

Matteo Sonza Reorda , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
Giovanni Squillero , Politecnico di Torino
pp. 321
Session 2.3.3: System Performance Issues

FPGA-Based Internet Protocol Version 6 Router (Abstract)

Ayman Kayssi , American University of Beirut
Mohamad Mansour , American University of Beirut
pp. 334

Partitioning in Time : A Paradigm for Reconfigurable Computing (Abstract)

Dinesh Bhatia , University of Cincinnati
Karthikeya M. Gajjala Purna , University of Cincinnati
pp. 340
Session 2.3.4: Asynchronous Design Techniques

Pulse-Mode Macromodular Systems (Abstract)

Stephen H. Unger , Columbia University
Luis A. Plana , Universidad Polit?cnica
pp. 348

Rapid Prototyping of Self-timed Circuits (Abstract)

S.W. Moore , University of Cambridge
P. Robinson , University of Cambridge
pp. 360
Session 2.4.1: Cache and Memory Systems

Evaluating the Performance of Active Cache Management Schemes (Abstract)

Edward S. Davidson , The University of Michigan
Gary S. Tyson , The University of Michigan
Jude A. Rivers , The University of Michigan
Edward S. Tam , The University of Michigan
Vijayalakshmi Srinivasan , The University of Michigan
pp. 368

Data Cache Parameter Measurements (Abstract)

Enyou Li , University of Auckland
Clark Thomborson , University of Auckland
pp. 376
Session 2.4.2: Timing and Synthesis Verification

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis (Abstract)

Rajesh Radhakrishnan , University of Cincinnati
Elena Teica , University of Cincinnati
Naren Narasimhan , University of Cincinnati
Sriram Govindarajan , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 392
Session 2.4.3: Low Power/High Efficiency Networks

Low-Power Radix-8 Divider (Abstract)

Tomas Lang , University of California, Irvine
Alberto Nannarelli , University of California, Irvine
pp. 420

A Self-Timed Real-Time Sorting Network (Abstract)

Robert Fairlie-Cuninghame , University of California, San Diego
Rene L. Cruz , University of California, San Diego
Kenneth Y. Yun , University of California, San Diego
Kevin W. James , University of California, San Diego
Supratik Chakraborty , Stanford University
pp. 427
Session 2.4.4: High-Level Synthesis
Session 2.5.1: Panel
Dinner Presentation
Session 3.1: Plenary
Session 3.2.1: Embedded Tutorial
Session 3.2.2: VLIW and Parallel Processing

Circular Buffered Switch Design with Wormhole Routing and Virtual Channels (Abstract)

Laxmi Bhuyan , Texas A&M University
Marius Pirvu , Texas A&M University
Nan Ni , Texas A&M University
pp. 466

The Effects of Explicitly Parallel Mechanisms on the Multi-ALU Processor Cluster Pipeline (Abstract)

William J. Dally , Stanford University
Andrew Chang , Stanford University
Stephen W. Keckler , Stanford University
Whay S. Lee , Massachusetts Institute of Technology
Nicholas P. Carter , Stanford University
pp. 474
Session 3.2.3: ATPG

On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , University of Iowa
Xijiang Lin , University of Iowa
pp. 498

Enhancing Topological ATPG with High-Level Information and Symbolic Techniques (Abstract)

Matteo Sonza Reorda , Politecnico di Torino
Roberto Vietti , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
Elizabeth M. Rudnick , University Illinois
Janak H. Patel , University Illinois
pp. 504

An Exact Solution to the Minimum Size Test Pattern Problem (Abstract)

Paulo F. Flores , Instituto Superior Tecnico/INESC
Joao P. Marques Silva , Instituto Superior Tecnico/INESC
Horacio C. Neto , Instituto Superior Tecnico/INESC
pp. 510

Using Regression Analysis for GA-Based ATPG Parameter Optimization (Abstract)

R.D. (Shawn) Blanton , Carnegie Mellon University
William E. Dougherty , Carnegie Mellon University
pp. 516
Session 3.2.4: Timing and Power Analysis

Practical Use of Transition Mode Delay to Solve the Problems of Floating Mode Delay under Highly Correlated Input Streams (Abstract)

Hoon Choi , Korea Advanced Institute of Science and Technology,
Seung Ho Hwang , Korea Advanced Institute of Science and Technology,
pp. 536

A Fractal Compaction Algorithm for Efficient Power Estimation (Abstract)

Radjakichenin Radjassamy , The University of Arizona
Jo Dale Carothers , The University of Arizona
pp. 542
Session 3.3.1: Performance Analysis and Microarchitecture

Code Coalescing Unit: A Mechanism to Facilitate Load Store Data Communication (Abstract)

Lizy John , The University of Texas at Austin
Francis Matus , The University of Texas at Austin
Craig Chase , The University of Texas at Austin
Yin Teh , The University of Texas at Austin
pp. 550

Profiling for Input Predictable Threads (Abstract)

D. Scott Wills , Georgia Institute of Technology
Lucian Codrescu , Georgia Institute of Technology
pp. 558
Session 3.3.2: Mixed Signal Testing
Session 3.3.3: Co-Design

Buffer Size Driven Partitioning for HW/SW Co-Design (PDF)

Walling R. Cyre , Virginia Tech
Sadiq M. Sait , King Fahd University of Petroleum & Minerals
pp. 596

Scheduling Under Data and Control Dependencies for Heterogeneous Architectures (Abstract)

Alex Doboli , University of Cincinnati
Petru Eles , Linkoping University
pp. 602

Integrated Partitioning and Scheduling for Hardware/Software Co-design (Abstract)

Huiqun Liu , University of Texas at Austin
D. F. Wong , University of Texas at Austin
pp. 609
Session 3.3.4: Place and Route

Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization (Abstract)

Aiguo Lu , LSI Logic Corporation
Hans Eisenmann , Technical University of Munich
Frank M. Johannes , Technical University of Munich
Guenter Stenz , Technical University of Munich
pp. 616

Learning as Applied to Stochastic Optimization for Standard Cell Placement (Abstract)

Richard A. Newton , University of California at Berkeley
Lixin Su , University of California at Berkeley
Bradley S. Peters , University of California at Berkeley
Wray Buntine , University of California at Berkeley
pp. 622

Timing-Driven Routing for Symmetrical-Array-Based FPGAs (Abstract)

Kai Zhu , Triscend Corp.
Yao-Wen Chang , National Chiao Tung University
D.F. Wong , University of Texas at Austin
pp. 628

Author Index (PDF)

pp. 642
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