Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) (1998)
Oct. 5, 1998 to Oct. 5, 1998
Fulvio Corno , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Roberto Vietti , Politecnico di Torino
Janak H. Patel , University Illinois
Elizabeth M. Rudnick , University Illinois
This paper proposes a method to enhance topological ATPG algorithms by exploiting some information computed through symbolic techniques. Since symbolic techniques can only be applied to small circuits, suitable circuit portions (named macros) are first selected, and then symbolic techniques are used to analyze their state graphs. The topological ATPG algorithm benefits from this analysis to bound its search tree. Experimental results show that the proposed approach is effective in reducing the required CPU time and increasing both the Fault Coverage and the Fault Efficiency. When high-level information about the circuit behavior and structure is available, it can be fruitfully exploited for macro selection.
Binary Decision Diagrams, Automatic Test Pattern Generation, Hybrid ATPG approaches
M. Sonza Reorda, R. Vietti, F. Corno, E. M. Rudnick and J. H. Patel, "Enhancing Topological ATPG with High-Level Information and Symbolic Techniques," Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)(ICCD), Austin, Texas, 1998, pp. 504.