The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (1997)
Austin, TX
Oct. 12, 1997 to Oct. 15, 1997
ISSN: 1063-6404
ISBN: 0-8186-8206-X
TABLE OF CONTENTS
Session 1.1: Keynote Speech

Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures (Abstract)

Katherine Yelick , Computer Science Division University of California, Berkeley CA
Kimberly Keeton , Computer Science Division University of California, Berkeley CA
Aaron Brown , Computer Science Division University of California, Berkeley CA
Richard Fromm , Computer Science Division University of California, Berkeley CA
Krste Asanovic , Computer Science Division University of California, Berkeley CA
Benjamin Gribstad , Computer Science Division University of California, Berkeley CA
Jason Golbus , Computer Science Division University of California, Berkeley CA
Stylianos Perissakis , Computer Science Division University of California, Berkeley CA
Randi Thomas , Computer Science Division University of California, Berkeley CA
Christoforos Kozyrakis , Computer Science Division University of California, Berkeley CA
David Martin , Computer Science Division University of California, Berkeley CA
Noah Treuhaft , Computer Science Division University of California, Berkeley CA
David Patterson , Computer Science Division University of California, Berkeley CA
pp. 2
Session 1.2: CAD Plenary
Session 1.3.1: Special Session: Industrial Applications of Formal Verification

Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor (Abstract)

S. Jain , Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
G.P. Bischoff , Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
K.S. Brace , Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
R. Razdan , Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
pp. 16

Intertwined development and formal verification of a 60/spl times/ bus model (Abstract)

M. Kaufmann , Motorola Inc., Austin, TX, USA
C. Pixley , Motorola Inc., Austin, TX, USA
pp. 25

Formally specifying and mechanically verifying programs for the Motorola complex arithmetic processor DSP (Abstract)

C. Brock , Comput.. Logic Inc., Austin, TX, USA
W.A. Hunt, Jr. , Comput.. Logic Inc., Austin, TX, USA
pp. 31

BIST-based fault diagnosis in the presence of embedded memories (Abstract)

J. Savir , Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 37

Built-In Self Test for Content Addressable Memories (Abstract)

Yong-Seok Kang , Yonsei University
Jong-Cheol Lee , Yonsei University
Sungho Kang , Yonsei University
pp. 48

Pseudo-random pattern testing of bridging faults (Abstract)

E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
N.A. Touba , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 54
Session 1.3.3: Simulation and Power Estimation

Novel Simulation of Deep-Submicron MOSFET Circuits (Abstract)

Serban Bruma , CAS Group, Technical University DELFT
Ralph H.J.M. Otten , CAS Group, Technical University DELFT
pp. 62

Time-stamped transition density for the estimation of delay dependent switching activities (Abstract)

Seung Ho Hwang , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Hoon Choi , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
pp. 68

Power compiler: a gate-level power optimization and synthesis system (Abstract)

B. Chen , Synopsys Inc., Mountain View, CA, USA
I. Nedelchev , Synopsys Inc., Mountain View, CA, USA
pp. 74
Session 1.3.4: Branch Prediction

Design optimization for high-speed per-address two-level branch predictors (Abstract)

T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
I.-C.K. Chen , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
M. Postiff , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Chih-Chieh Lee , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 88

PA-8000: a case study of static and dynamic branch prediction (Abstract)

C. Burch , Hewlett-Packard Co., Colorado Springs, CO, USA
pp. 97
Session 1.4.1: New Techniques for Gate-Sizing and Retiming

Discrete drive selection for continuous sizing (Abstract)

L.P.P.P. van Ginneken , Synopsys Inc., Mountain View, CA, USA
N. Shenoy , Synopsys Inc., Mountain View, CA, USA
R. Haddad , Synopsys Inc., Mountain View, CA, USA
pp. 110

Continuous retiming: algorithms and applications (Abstract)

Peichen Pan , Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA
pp. 116

Optimal clock period clustering for sequential circuits with retiming (Abstract)

Peichen Pan , Intel Corp., Folsom, CA, USA
C.L. Liu , Intel Corp., Folsom, CA, USA
A.K. Karandikar , Intel Corp., Folsom, CA, USA
pp. 122
Session 1.4.2: Circuit Modeling

Comparison between nMOS pass transistor logic style vs. CMOS complementary cells (Abstract)

Xunwei Wu , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
R. Mehrotra , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 130

Circuit-based description and modeling of electromagnetic noise effects in packaged low-power electronics (Abstract)

W. Pinello , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
A.C. Cangellaris , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
A. Ruehli , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 136

Transistor-Level Sizing and Timing Verification of Domino Circuits in the Power PC(TM) Microprocessor (Abstract)

J. Dunning , Somerset Design Center, Motorola Inc.
A. Dharchoudhury , High Performance Design Technology, Unified Design Systems Lab
S. Pullela , High Performance Design Technology, Unified Design Systems Lab
D. Blaauw , High Performance Design Technology, Unified Design Systems Lab
J. Norton , High Performance Design Technology, Unified Design Systems Lab
pp. 143
Session 1.4.3: Novel Architectures

Architectural adaptation for application-specific locality optimizations (Abstract)

A.A. Chien , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
M. Schulzt , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
R.K. Gupta , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Xingbin Zhang , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
A. Dasdan , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 150

A New Processor Architecture for Digital Signal Transport Systems (Abstract)

Toshiaki Miyazaki , NTT Optical Network Systems Laboratories
Kenji Ishii , NTT Optical Network Systems Laboratories
Kazuhiro Shirakawa , NTT Optical Network Systems Laboratories
Hiroshi Nakada , NTT Optical Network Systems Laboratories
Akihiro Tsutsui , NTT Optical Network Systems Laboratories
Minoru Inamori , NTT Optical Network Systems Laboratories
pp. 157
Short Papers

PROPHID: a heterogeneous multi-processor architecture for multimedia (Abstract)

A.H. Timmer , Philips Res. Lab., Eindhoven, Netherlands
J.A.J. Leijten , Philips Res. Lab., Eindhoven, Netherlands
J.L. van Meerbergen , Philips Res. Lab., Eindhoven, Netherlands
J.A.G. Jess , Philips Res. Lab., Eindhoven, Netherlands
pp. 164

Enhanced compression techniques to simplify program decompression and execution (Abstract)

R. Smith , Motorola Inc., Austin, TX, USA
M. Breternitz, Jr. , Motorola Inc., Austin, TX, USA
pp. 170
Session 1.4.4: Low Power Architectures

A low power approach to floating point adder design (Abstract)

A.J. Al-Khalili , Concordia Univ., Montreal, Que., Canada
R.V.K. Pillai , Concordia Univ., Montreal, Que., Canada
D. Al-Khalili , Concordia Univ., Montreal, Que., Canada
pp. 178

Design and implementation of low-power digit-serial multipliers (Abstract)

Yun-Nan Chang , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
J.H. Satyanarayana , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 186

On complexity reduction of FIR digital filters using constrained least squares solution (Abstract)

K. Roy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Muhammad , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 196
Session 1.5.1: Timing Optimization for Deep Submicron Technology

Post-layout circuit speed-up by event elimination (Abstract)

M. Pedram , Cadence Design Syst. Inc., San Jose, CA, USA
H. Vaishnav , Cadence Design Syst. Inc., San Jose, CA, USA
Chi-Keung Lee , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 211

Clustering and load balancing for buffered clock tree synthesis (Abstract)

N. Menezes , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
A.D. Mehta , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Yao-Ping Chen , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 217

CMOS gate delay models for general RLC loading (Abstract)

F. Dartu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Arunachalam , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 224
Session 1.5.2: Special Session: The G4 S/390 Microprocessor

Design methodology for the high-performance G4 S/390 microprocessor (Abstract)

R. Hatch , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Northrop , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Carey , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D.K. Beece , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
K.L. Shepard , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 232

A high-frequency custom CMOS S/390 microprocessor (Abstract)

C.F. Webb , IBM Corp., Poughkeepsie, NY, USA
J.S. Liptay , IBM Corp., Poughkeepsie, NY, USA
pp. 241

High performance CMOS circuit techniques for the G-4 S/390 microprocessor (Abstract)

L. Sigal , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
B. Curran , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Y. Chan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
J. Warnock , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 247

A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor (Abstract)

A. Tuminaro , IBM Systems 390 Division, Poughkeepsie, NY
pp. 253
Session 1.5.3: Multiprocessor Communication

A comparative evaluation of hierarchical network architecture of the HP-Convex Exemplar (Abstract)

Xiaodong Zhang , Texas Univ., San Antonio, TX, USA
J.M. Hoover, Jr. , Texas Univ., San Antonio, TX, USA
R. Castaneda , Texas Univ., San Antonio, TX, USA
pp. 258

Effect of message length and processor speed on the performance of the bidirectional ring-based multiprocessor (Abstract)

H. Oi , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 267

An approach to network caching for multimedia objects (Abstract)

M. Kozuch , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 273

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip (Abstract)

A. Satoh , IBM Research, Tokyo Research Laboratory
R. Joshi , IBM Thomas J. Watson Research Center
W. K. Luk , IBM Thomas J. Watson Research Center
W. Hwang , IBM Thomas J. Watson Research Center
B. El-Kareh , IBM Power PC Microprocessor Development
P. Xiao , IBM Thomas J. Watson Research Center
T. Kirihata , IBM Semiconductor Research and Development Center
Y. Katayama , IBM Research, Tokyo Research Laboratory
M. Wordeman , IBM Semiconductor Research and Development Center
S. Munetoh , IBM Research, Tokyo Research Laboratory
H. Wong , IBM Semiconductor Research and Development Center
pp. 279
Session 1.5.4: Asynchronous Architectures

TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model (Abstract)

T. Nanya , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
M. Ozawa , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
M. Imai , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
A. Takamura , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
Y. Ueno , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
I. Fukasaku , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
M. Kuwako , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
T. Fujii , Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
pp. 288

An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures (Abstract)

David Lloyd , University of Manchester, Manchester, UK
Andrew Davey , North Lincoln College
pp. 295

Asynchronous Wrapper for Heterogeneous Systems (Abstract)

David S. Bormann , Imperial College of Science, Technology and Medicine University of London
Peter Y. K. Cheung , Imperial College of Science, Technology and Medicine University of London
pp. 307
Session 1.6.1
Session 1.6.2
Session 2.1 Design and Test Plenary
Session 2.2.1: Binary Decision Diagrams

Equivalence checking using abstract BDDs (Abstract)

M. Minea , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
E.M. Clarke , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
Y. Lu , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Jha , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 332

Speeding up variable reordering of OBDDs (Abstract)

A. Slobodova , Trier Univ., Germany
C. Meinel , Trier Univ., Germany
pp. 338

Dynamic reordering in a breadth-first manipulation based BDD package: challenges and solutions (Abstract)

W. Gosti , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincenteili , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Ranjan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 344

Timed binary decision diagrams (Abstract)

R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Yuhong Zhao , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Yinghua Min , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Zhongcheng Li , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 352
Session 2.2.2: Advanced Test Topics

Vector restoration based static compaction of test sequences for synchronous sequential circuits (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 360

Nonenumerative path delay fault coverage estimation with optimal algorithms (Abstract)

S. Tragoudas , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
D. Karayiannis , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
D. Kagaris , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 366

Properties of the input pattern fault model (Abstract)

R.D. Blanton , Center for Electron. Design Autom., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Hayes , Center for Electron. Design Autom., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 372
Session 2.2.3: Embedded Software and Systems

Real-Time Operating Systems for Embedded Computing (Abstract)

Wayne Wolf , Princeton University
Miodrag Potkonjak , Department of Computer Science, UCLA
Yanbing Li , Princeton University
pp. 388

Allocation and Data Arrival Design of Hard Real-time Systems (Abstract)

Wayne Wolf , Princeton University
David L. Rhodes , US Army CECOM, RD&E Center
pp. 393

Improving design turnaround time via two-levels HW/SW co-simulation (Abstract)

F. Salice , Central Res. Lab., ITALTEL-SIT, Italy
A. Allara , Central Res. Lab., ITALTEL-SIT, Italy
S. Filipponi , Central Res. Lab., ITALTEL-SIT, Italy
W. Fornaciari , Central Res. Lab., ITALTEL-SIT, Italy
D. Sciuto , Central Res. Lab., ITALTEL-SIT, Italy
pp. 400
Session 2.2.4: Low Power Issues

Power constrained design of multiprocessor interconnection networks (Abstract)

D.E. Schimmel , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
C.S. Patel , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S.M. Chai , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S. Yalamanchili , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 408

Memory traffic and data cache behavior of an MPEG-2 software decoder (Abstract)

P. Soderquist , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
M. Leeser , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 417

Asynchronous transpose-matrix architectures (Abstract)

P. Kudva , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
J.A. Tierno , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 423

A low power smart vision system based on active pixel sensor integrated with programmable neural processor (Abstract)

B. Pain , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Wai-Chi Fang , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
B.J. Sheu , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Guang Yang , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 429
Session 2.3.1: Formal Verification Methods

Formal verification of the HAL S1 System cache coherence protocol (Abstract)

M. Fujita , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
A.J. Hu , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
C. Wilson , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 438

A Survey of Techniques for Formal Verification of Combinational Circuits (Abstract)

Amit Narayan , University of California, Berkeley
Jawahar Jain , Fujitsu Laboratories of America
M. Fujita , Fujitsu Laboratories of America
A. Sangiovanni-Vincentelli , University of California, Berkeley
pp. 445

Checking formal specifications under simulation (Abstract)

W. Canfield , CAE, Austin, TX, USA
E.A. Emerson , CAE, Austin, TX, USA
A. Saha , CAE, Austin, TX, USA
pp. 455
Session 2.3.2: Mixed Signal Design and Test

Development of hierarchical testability design methodologies for analog/mixed-signal integrated circuits (Abstract)

Cheng-Ping Wang , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Chin-Long Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 468

A novel test set design for parametric testing of analog and mixed-signal circuits (Abstract)

A. Ramachandran , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Jin Chen , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 474
Session 2.3.3: FPGA Design

On the Construction of Universal Series-Parallel Functions for Logic Module Design (Abstract)

D.F. Wong , The University of Texas at Austin
F.Y. Young , The University of Texas at Austin
pp. 482

A universal Pezaris array multiplier generator for SRAM-based FPGAs (Abstract)

E. Barke , Inst. of Microelectron. Syst., Hannover Univ., Germany
J. Stohmann , Inst. of Microelectron. Syst., Hannover Univ., Germany
pp. 489

Channel Segmentation Design for Symmetrical FPGAs (Abstract)

D. F. Wong , University of Texas at Austin
Wai-Kei Mak , University of Texas at Austin
pp. 496
Session 2.3.4: Cache Technology I

Multi-column implementations for cache associativity (Abstract)

Xiaodong Zhang , Changsha Inst. of Technol., Hunan, China
Chenxi Zhang , Changsha Inst. of Technol., Hunan, China
Yong Yan , Changsha Inst. of Technol., Hunan, China
pp. 504

Design and performance evaluation of a cache assist to implement selective caching (Abstract)

A. Subramanian , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
L.K. John , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 510

On effective data supply for multi-issue processors (Abstract)

E.S. Tam , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.A. Rivers , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 519
Session 2.4.1: Embedded Tutorial

Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits (Abstract)

K. L. Shepard , IBM Research Division, T. J. Watson Research Center
pp. 532
Session 2.4.2: Fault Diagnosis

First test results of system level fault tolerant design validation through laser fault injection (Abstract)

J.R. Samson, Jr. , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
T. Smith , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
F.J. Falquez , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
W.A. Moreno , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 544

A TSC evaluation function for combinational circuits (Abstract)

F. Salice , Dipt. di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipt. di Elettronica, Politecnico di Milano, Italy
C. Bolchini , Dipt. di Elettronica, Politecnico di Milano, Italy
pp. 555
Session 2.4.3: Special Session: Low Power Design Issues
Session 2.4.4: Cache Technology II

Fast cache access with full-map block directory (Abstract)

W.W. Hsu , CISE Dept., Florida Univ., Gainesville, FL, USA
S. Ong , CISE Dept., Florida Univ., Gainesville, FL, USA
Kih-Kwon Peir , CISE Dept., Florida Univ., Gainesville, FL, USA
H. Young , CISE Dept., Florida Univ., Gainesville, FL, USA
pp. 578

A data alignment technique for improving cache performance (Abstract)

N.D. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
H. Nakamura , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
P. Ranjan Panda , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 587

Instruction prefetching using branch prediction information (Abstract)

T.N. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
I-Cheng K. Chen , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Chih-Chieh Lee , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 593
Session 3.1: Architecture & Algorithm Plenary

Is wireless data dead? (Abstract)

R.H. Katz , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 604
Session 3.2.1: Layout Partitioning and Synthesis

An efficient multi-way algorithm for balanced partitioning of VLSI circuits (Abstract)

N. Park , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
J. Tong , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
X. Tan , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
P. Tan , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
F. Lombardi , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
pp. 608

Partitioning under timing and area constraints (Abstract)

G. Tumbush , Dept. of Electron. Comput., Cincinnati Univ., OH, USA
D. Bhatia , Dept. of Electron. Comput., Cincinnati Univ., OH, USA
pp. 614

A parallel circuit-partitioned algorithm for timing driven cell placement (Abstract)

P. Banerjee , Sierra Vista Res., Los Gatos, CA, USA
J.A. Chandy , Sierra Vista Res., Los Gatos, CA, USA
pp. 621

Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation (Abstract)

D.F. Wong , University of Texas at Austin
Hai Zhou , University of Texas at Austin
pp. 628
Session 3.2.2: Design for Testability & Test Synthesis

High level test synthesis across the boundary of behavioral and structural domains (Abstract)

M. Baklashov , Rockwell Semicond. Syst., Newport Beach, CA, USA
C.A. Papachristou , Rockwell Semicond. Syst., Newport Beach, CA, USA
K. Lai , Rockwell Semicond. Syst., Newport Beach, CA, USA
pp. 636

Power driven partial scan (Abstract)

Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Ming-Chang Nien , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 642

Synthesis of delay verifiable sequential circuits using partial enhanced scan (Abstract)

R.C. Takumalla , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
P.R. Menon , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 648

Application of a testing framework to VHDL descriptions at different abstraction levels (Abstract)

F. Ferrandi , Dipt. di Elettronica, Politecnico di Milano, Italy
F. Fummi , Dipt. di Elettronica, Politecnico di Milano, Italy
G. Buonanno , Dipt. di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipt. di Elettronica, Politecnico di Milano, Italy
M. Bacis , Dipt. di Elettronica, Politecnico di Milano, Italy
L. Gerli , Dipt. di Elettronica, Politecnico di Milano, Italy
pp. 654
Session 3.2.3: Embedded Tutorial
Session 3.2.4: Arithmetics

Benchmarking and analysis of architectures for CAD applications (Abstract)

R.K. Ranjan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.H. Katz , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Qadeer , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Meehrotra , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 670

Fast Low-Energy VLSI Binary Addition (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis, MN
pp. 676

A floating-point divider using redundant binary circuits and an asynchronous clock scheme (Abstract)

K. Mashiko , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
H. Makino , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
H. Hamano , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
H. Suzuki , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
pp. 685

Parallel-array implementations of a non-restoring square root algorithm (Abstract)

Wanming Chu , Comput. Archit. Lab., Univ. of Aizu, Japan
Yamin Li , Comput. Archit. Lab., Univ. of Aizu, Japan
pp. 690
Session 3.3.1: Asynchronous Design

Optimizing CMOS Implementations of the C-element (Abstract)

Jo C. Ebergen , Sun Microsystems Laboratories
Maitham Shams , University of Waterloo
Mohamed I. Elmasry , University of Waterloo
pp. 700

A doubly-latched asynchronous pipeline (Abstract)

R. Kol , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
R. Ginosar , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
pp. 706

A pulse-to-static conversion latch with a self-timed control circuit (Abstract)

R.V. Joshi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
W.H. Henkels , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Wei Hwang , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 712
Session 3.3.2: Special Session: Interconnect Modeling & Repeater Methodologies

Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect (Abstract)

Norman Chang , Hewlett-Packard Laboratories
Khalid Rahmat , Hewlett-Packard Laboratories
Soo-Young Oh , Hewlett-Packard Laboratories
Valery Kanevsky , Hewlett-Packard Laboratories
O. Sam Nakagawa , Hewlett-Packard Laboratories
pp. 720

A repeater optimization methodology for deep sub-micron, high-performance processors (Abstract)

P. Srivastava , Texas Instrum. Inc., Dallas, TX, USA
D. Li , Texas Instrum. Inc., Dallas, TX, USA
A. Pua , Texas Instrum. Inc., Dallas, TX, USA
U. Ko , Texas Instrum. Inc., Dallas, TX, USA
pp. 726

Critical voltage transition logic: an ultrafast CMOS logic family (Abstract)

B.S. Carlson , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Zheng Zhu , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 732
Session 3.3.3: Finite-State Machine and High-Level Synthesis

Estimation of maximum power for sequential circuits considering spurious transitions (Abstract)

Chuan-Yu Wang , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 746

Dynamic bounding of successor force computations in the force directed list scheduling algorithm (Abstract)

S. Govindarajan , Lab. for Digital Design Environ., Cincinnati Univ., OH, USA
R. Vemuri , Lab. for Digital Design Environ., Cincinnati Univ., OH, USA
pp. 752

Author Index (PDF)

pp. 758
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