The Community for Technology Leaders
2012 IEEE 30th International Conference on Computer Design (ICCD) (1996)
Austin, TX
Oct. 7, 1996 to Oct. 9, 1996
ISSN: 1063-6404
ISBN: 0-8186-7554-3
TABLE OF CONTENTS

Program Committee (PDF)

pp. xvii

Reviewers (PDF)

pp. xx
Session 1.3.1: Verification, Chair: Carl Pixley, Motorola, Inc.

Enhancing FSM Traversal by Temporary Re-Encoding (Abstract)

Luciano Lavagno , Politecnico di Torino
Massimo Poncino , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Gianpiero Cabodi , Politecnico di Torino
Ellen Sentovicha , Ecole des Mines de Paris
Stefano Quer , Politecnico di Torino
Paolo Camurati , Universita` di Udine
pp. 6
Session 1.3.2: Design for Test, Chair: Sumit Dasgupta, SEMATECH

A multiseed counter TPG with performance guarantee (Abstract)

S. Tragoudas , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
D. Kagaris , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 34

Design for testability of integrated operational amplifiers using oscillation-test strategy (Abstract)

S. Sunter , Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
B. Kaminska , Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
K. Arabi , Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
pp. 40

A Design For Test Perspective on I/O Management (Abstract)

Kamran Zarrineh , IBM Microelectronics Test Design Automation
Vivek Chickermane , IBM Microelectronics Test Design Automation
pp. 46
Session 1.3.3: Panel: Opportunities and Pitfalls in HDL-Based System Design
Session 1.3.4: Panel: Issues on the Architecture and the Design of Distributed Shared Memory Systems

Issues on the architecture and the design of distributed shared memory systems (PDF)

S.J. Wallach , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Nian-Feng Tzeng , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 60

Design issues for distributed shared-memory systems (PDF)

D.E. Lenoski , Div. of Adv. Syst., Silicon Graphics Comput. Syst., Mountain View, CA, USA
pp. 62

The Tempest approach to distributed shared memory (PDF)

D.A. Wood , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
M.D. Hill , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
J.R. Larus , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 63
Session 1.4.1: Novel Aspects of Scheduling, Chair: Masahiro Fujeta, Fujitsu Laboratories of America, Inc.

Multiplexor Network Generation in High Level Synthesis (Abstract)

Yung-Ming Fang , University of Texas
D. F. Wong , University of Texas
pp. 78
Session 1.4.2: Special Session: Multimedia Systems, Chair and Organizer: Bing Sheu, University of Southern California

Multimodal query support in database servers (Abstract)

G. Au , NCR Corp., Murray Hill, NJ, USA
W. O'Connell , NCR Corp., Murray Hill, NJ, USA
D. Schrader , NCR Corp., Murray Hill, NJ, USA
pp. 86

Evaluation of high speed LAN protocols as multimedia carriers (Abstract)

J. Wang , Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
Yu-Feng Chung , Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
Teng-Sheng Moh , Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
W.M. Moh , Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
pp. 93
Session 1.4.3: System Design Aspects, Chair: Rabindra (Rob) Roy, NEC USA Research Laboratories

Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs (Abstract)

A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 112

Pausible Clocking: A First Step Toward Heterogeneous Systems (Abstract)

Kenneth Y. Yun , University of California, San Diego
Ryan P. Donohue , University of California, San Diego
pp. 118
Session 1.4.4: Panel
Poster Session, Chair: Craig Hunter, Motorola, Inc.

Testing of embedded A/D converters in mixed-signal circuit (PDF)

N. Ben-Hamida , Ecole Polytech., Montreal, Que., Canada
B. Ayari , Ecole Polytech., Montreal, Que., Canada
B. Kaminska , Ecole Polytech., Montreal, Que., Canada
pp. 135

A VLSI array architecture with dynamic frequency clocking (Abstract)

N. Ranganathan , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Bhavanishankar , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Vijaykrishnan , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 137

An integrated microspacecraft avionics architecture using 3D multichip module building blocks (Abstract)

Wai-Chi Fang , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
L. Alkalai , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 141

An output-shared buffer ATM switch (PDF)

Jin Li , Dept. of Adv. Archit. Dev., Adv. Micro Devices Inc., Austin, TX, USA
pp. 147

A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management (Abstract)

Ming-Der Shieh , National Yunlin Institute of Technology
Chie Dou , National Yunlin Institute of Technology
pp. 149
Session 2.1.1: Design and Test Plenary, Chair: Magdy Abadir, Motorola, Inc.
Session 2.2.1: Data Communication, Chair: John Trotter, AT&T Bell Laboratories

Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network (Abstract)

Scott Wills , Georgia Institute of Technology
Thomas Gaylord , Georgia Institute of Technology
Jose L. Cruz-Rivera , University of Puerto Rico-Mayaguez
Elias Glytsis , Georgia Institute of Technology
pp. 165

MMPacking: A Load and Storage Balancing Algorithm for Distributed Multimedia Servers (Abstract)

D. N. Serpanos , IBM Research Division T.J. Watson Research Ctr.
L. Georgiadis , Univ. of Thessaloniki
T. Bouloutas , Bank of Boston
pp. 170
Session 2.2.2: Design Automation for Embedded Systems, Chair: Rolf Ernst, Technical University of Braunschweig
Session 2.2.3: Branch Prediction, Chair: Jim Bondi, Texas Instruments

Profile-Driven Generation of Trace Samples (Abstract)

Ravi Nair , IBM Thomas J. Watson Research Center
Pradeep K. Dubey , IBM Thomas J. Watson Research Center
pp. 217

Branch-Directed and Stride-Based Data Cache Prefetching (Abstract)

Yue Liu , Northeastern University
David R. Kaeli , Northeastern University
pp. 225
Session 2.2.4: Automatic Test Pattern Generation, Chairs: Bob Molyneaux, IBM Corporation; Hoon Chang, Soong-Sil University of Korea

A Better ATPG Algorithm and Its Design Principles (Abstract)

Li-C. Wang , University of Texas at Austin
M. Ray Mercer , Texas A&M University
pp. 248

Modeling the Difficulty of Sequential Automatic Test Pattern Generation (Abstract)

Thomas E. Marchok , Carnegie Mellon University
Wojciech Maly , Carnegie Mellon University
pp. 261
Session 2.3.1: VLSI Layout, Chair: Andreas Kuehlmann, IBM Corporation

Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technology (Abstract)

Neil A Thacker , University of Sheffield
David J Prendergast , University of Sheffield
Steven P Larcombe , University of Sheffield
Peter A Ivey , University of Sheffield
pp. 274
Session 2.3.2: Special Session: Motorola Processor Design Session Chair: Nasr Ullah, Organizer: Andy Wolfe
Session 2.3.3: Embedded Systems Tutorial, Chair: Rolf Ernst, Technical University of Braunschweig
Session 2.3.4: VLSI Technology and Design, Chair: Kit Cham, Hewlett-Packard

Clock-Delayed Domino for Adder and Combinational Logic Design (Abstract)

Gin Yee , University of Washington
Carl Sechen , University of Washington
pp. 332
Session 2.4.1: Panel
Session 2.4.2: Panel
Session 3.1.1: Special Session, Chair: Wayne Wolf, Princeton University

DNA computations can have global memory (Abstract)

R.J. Lipton , Princeton Univ., NJ, USA
pp. 344
Session 3.2.1: Verification II, Chair: Gabriel Bischoff, DAC

A formal verification technique for embedded software (Abstract)

O. Thiry , IMEC, Katholieke Univ., Leuven, Belgium
L. Claesen , IMEC, Katholieke Univ., Leuven, Belgium
pp. 352

Binary decision diagrams on network of workstations (Abstract)

R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J.V. Sanghavi , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Ranjan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 358

The use of random simulation in formal verification (Abstract)

A. Mets , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
F. Krohm , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Kuchlmann , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 371
Session 3.2.2: Minimization Techniques, Chair: Shantanu Ganguly, Motorola, Inc.

Implicit Test Sequences Compaction for Decreasing Test Application Cost (Abstract)

Roberto Bevacqua , Politecnico di Milano
Fabrizio Ferrandi , Politecnico di Milano
Luca Guerrazzi , Politecnico di Milano
Franco Fummi , Politecnico di Milano
pp. 384

Dichotomy-based Model for FSM Power Minimization (Abstract)

Liang-Fang Chao , Iowa State University
Lakshmikant Bhupathi , Iowa State University
pp. 390

Optimal single probe traversal algorithm for testing of MCM substrate (Abstract)

A. Chatterjee , Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
C. Tovey , Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
R. Pendurkar , Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 396
Session 3.2.3: Panel
Session 3.2.4: Future Asynchronous Designs, Chair: Larry Pileggi, Carnegie Mellon University

Efficient Delay-Insensitive RSFQ Circuits (Abstract)

Priyadarsan Patra , Intel Corporation
Donald S. Fussell , The University of Texas at Austin
pp. 413
Session 3.3.1: Sequential Synthesis, Chair: Lukas van Ginneken, Synopsis, Inc.

Exact Dichotomy-based Constrained Encodin (Abstract)

Olivier Coudert , Synopsys, Inc.
C.-J. Richard Shi , University of Iowa
pp. 426

Latch Redundancy Removal Without Global Reset (Abstract)

Robert K. Brayton , University of California at Berkeley
Vigyan Singhal , Cadence Berkeley Labs
Shaz Qadeer , University of California at Berkeley
pp. 432

A Practical Algorithm for Retiming Level-Clocked Circuits (Abstract)

Sachin S. Sapatnekar , Iowa State University
Naresh Maheshwari , Iowa State University
pp. 440
Session 3.3.2: Integration Support, Chair: Gabriel Bischoff, DAC

A Method for Analog Circuits Visualization (Abstract)

Bogdan G. Arsintescu , Delft University of Technology
pp. 454
Session 3.3.3: Special Session

Can Trace-Driven Simulators Accurately Predict Superscalar Performance? (Abstract)

Andrew S. Huang , Carnegie Mellon University
Mikko H. Lipasti , Carnegie Mellon University
Bryan Black , Carnegie Mellon University
John Paul Shen , Carnegie Mellon University
pp. 478

The Augmint multiprocessor simulation toolkit for Intel x86 architectures (Abstract)

J. Torrellas , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
M. Michael , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
A. Sharma , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
A.-T. Nguyen , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 486
Session 3.3.4: VLSI Signal Processors, Chair: Jacob A. Abraham, University of Texas at Austin

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers (Abstract)

Leilei Song , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
J.H. Satyanarayana , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Yun-Nam Chang , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 492

A VLSI chip for image compression using variable block size segmentation (Abstract)

S.B. Aruru , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
K.R. Namuduri , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 500
Session 3.4.1: Architectural Issues in High Level Synthesis, Chair: Masahiro Fujita, Fujitsu Laboratories of America, Inc.

Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapaths (Abstract)

T.E. Fuhrman , Gen. Motors Res. Labs., Warren, MI, USA
H.F. Ugurdag , Gen. Motors Res. Labs., Warren, MI, USA
pp. 514

Synthesis of Multi-Dimensional Applications in VHDL (Abstract)

Nelson L. Passos , Midwestern State University
Edwin H.-M. Sha , University of Notre Dame
pp. 530
Session 3.4.2: Arithmetic Circuits, Chair: N. Ranganathan, University of South Florida

Early Zero Detection (Abstract)

D. N. Jayasimha , The Ohio State University
David R. Lutz , Bell Laboratories
pp. 545
Session 3.4.4: Synthesis for FPGAs, Chair: Timothy Kam, Intel Corporation

An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Design (Abstract)

Jason Cong , University of California, Los Angeles
Chang Wu , University of California, Los Angeles
pp. 572

Index of Authors (PDF)

pp. 587
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