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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors (1995)
Austin, Texas
Oct. 2, 1995 to Oct. 4, 1995
ISSN: 1063-6404
ISBN: 0-8186-7165-3
TABLE OF CONTENTS
Session 1.2.2: Architecture/Algorithms Plenary, Chair: Bing Sheu, University of Southern California, Los Angeles

Statistical generalization: theory and applications (Abstract)

B.W. Wah , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
A. Ieumwananonthachai , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Shu Yao , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Ting Yu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 4
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin

Signal propagation in high-speed MCM circuits (Abstract)

C. Truzzi , IMEC, Leuven, Belgium
E. Beyne , IMEC, Leuven, Belgium
E. Ringoot , IMEC, Leuven, Belgium
J. Peeters , IMEC, Leuven, Belgium
pp. 12

Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel (Abstract)

J.S.-H. Wang , Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
W.W.-M. Dai , Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
pp. 18

A CMOS gate array with dynamic-termination GTL I/O circuits (Abstract)

J. Kudoh , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
T. Takahashi , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Y. Umada , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
M. Kimura , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
S. Yamamoto , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Y. Ito , Device Dev. Center, Hitachi Ltd., Tokyo, Japan
pp. 25
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University

Precise exception handling for a self-timed processor (Abstract)

W.F. Richardson , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
E. Brunvand , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 32

Implementing a STARI chip (Abstract)

M.R. Greenstreet , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 38

A high-performance asynchronous SCSI controller (Abstract)

K.Y. Yun , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
D.L. Dill , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 44
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University

Performance assessment of embedded Hw/Sw systems (Abstract)

J.P. Calvez , IRESTE, Nantes, France
O. Pasquier , IRESTE, Nantes, France
pp. 52

A simulation environment for hardware-software codesign (Abstract)

S.L. Coumeri , Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Thomas , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 58

Performance estimation for real-time distributed embedded systems (Abstract)

T.Y. Yen , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 64
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories

Verifying the performance of the PCI local bus using symbolic techniques (Abstract)

S. Campos , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
E. Clarke , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Marrero , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Minea , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 72

Formal verification of a PowerPC microprocessor (Abstract)

D.P. Appenzeller , IBM Microelectron. Burlington, Essex Junction, VT, USA
A. Kuehlmann , IBM Microelectron. Burlington, Essex Junction, VT, USA
pp. 79

Extending VLSI design with higher-order logic (Abstract)

A. Chavan , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Shiu-Kai Chin , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
S. Ikram , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Jang Dae Kim , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Juin-Yeu Zu , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 85
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.

Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor (Abstract)

S. Wallace , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Dagli , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Bagherzadeh , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 96

A superscalar RISC processor with pseudo vector processing feature (Abstract)

K. Shimamura , Res. Lab., Hitachi Ltd., Japan
S. Tanaka , Res. Lab., Hitachi Ltd., Japan
T. Shimomura , Res. Lab., Hitachi Ltd., Japan
T. Hotta , Res. Lab., Hitachi Ltd., Japan
E. Kamada , Res. Lab., Hitachi Ltd., Japan
H. Sawamoto , Res. Lab., Hitachi Ltd., Japan
T. Shimizu , Res. Lab., Hitachi Ltd., Japan
K. Nakazawa , Res. Lab., Hitachi Ltd., Japan
pp. 102

The resource conflict methodology for early-stage design space exploration of superscalar RISC processors (Abstract)

J.-D. Wellman , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 110
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University

Design of an efficient power distribution network for the UltraSPARC-I microprocessor (Abstract)

A. Dalal , Sun Microsystems Inc., Mountain View, CA, USA
L. Lev , Sun Microsystems Inc., Mountain View, CA, USA
S. Mitra , Sun Microsystems Inc., Mountain View, CA, USA
pp. 118

Clock controller design in SuperSPARC II microprocessor (Abstract)

H. Hao , Sun Microsystems Inc., Mountain View, CA, USA
K. Bhabuthmal , Sun Microsystems Inc., Mountain View, CA, USA
pp. 124

Incas: a cycle accurate model of UltraSPARC (Abstract)

G. Maturana , SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
J.L. Ball , SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
J. Gee , SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
A. Iyer , SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
J.M. O'Connor , SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
pp. 130
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola

Accurate device modeling techniques for efficient timing simulation of integrated circuits (Abstract)

A. Devgan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 138

Execution-time profiling for multiple-process behavioral synthesis (Abstract)

J.K. Adams , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.A. Miller , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 144

Emulation verification of the Motorola 68060 (Abstract)

J. Kumar , Adv. Design Technol., Motorola Inc., Austin, TX, USA
N. Strader , Adv. Design Technol., Motorola Inc., Austin, TX, USA
J. Freeman , Adv. Design Technol., Motorola Inc., Austin, TX, USA
M. Miller , Adv. Design Technol., Motorola Inc., Austin, TX, USA
pp. 150
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.

Testability analysis and insertion for RTL circuits based on pseudorandom BIST (Abstract)

J. Carletta , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 162

Efficient testability enhancement for combinational circuit (Abstract)

Y. Fang , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 168

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis (Abstract)

I. Ghosh , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Raghunathan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 173

Synthesis for testability of large complexity controllers (Abstract)

F. Fummi , Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica, Politecnico di Milano, Italy
M. Serro , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 180
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola

Multiprocessor design verification for the PowerPC 620 microprocessor (Abstract)

C. Montemayor , Motorola Inc., Austin, TX, USA
M. Sullivan , Motorola Inc., Austin, TX, USA
Jen-Tien Yen , Motorola Inc., Austin, TX, USA
P. Wilson , Motorola Inc., Austin, TX, USA
R. Evers , Motorola Inc., Austin, TX, USA
pp. 188

The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor (Abstract)

J. Slaton , Motorola Inc., Austin, TX, USA
S.P. Licht , Motorola Inc., Austin, TX, USA
M. Alexander , Motorola Inc., Austin, TX, USA
S. Reeves , Motorola Inc., Austin, TX, USA
R. Jessani , Motorola Inc., Austin, TX, USA
K.R. Kishore , Motorola Inc., Austin, TX, USA
pp. 196

A high performance bus and cache controller for PowerPC multiprocessing systems (Abstract)

M.S. Allen , Somerset Design Center, Austin, TX, USA
W.K. Lewchuk , Somerset Design Center, Austin, TX, USA
J.D. Coddington , Somerset Design Center, Austin, TX, USA
pp. 204

Performance monitoring on the PowerPC 604 microprocessor (Abstract)

C. Roth , IBM Corp., Austin, TX, USA
F. Levine , IBM Corp., Austin, TX, USA
E. Welbon , IBM Corp., Austin, TX, USA
pp. 212
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington

Thermal placement for high-performance multichip modules (Abstract)

Kai-Yuan Chao , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 218

EPNR: an energy-efficient automated layout synthesis package (Abstract)

G. Holt , Dept. of Comput. Sci., Iowa State Univ., Ames, IA, USA
A. Tyagi , Dept. of Comput. Sci., Iowa State Univ., Ames, IA, USA
pp. 224

PEPPER-a timing driven early floorplanner (Abstract)

V. Narayananan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D. LaPotin , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Gupta , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Vijayan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 230

Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning (Abstract)

Jin-Tai Yan , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 236
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America

An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions (Abstract)

T. Kozlowski , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
E.L. Dagless , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
J.M. Saul , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
pp. 244

Implicit state minimization of non-deterministic FSMs (Abstract)

T. Kam , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
T. Villa , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 250

Extending equivalence class computation to large FSMs (Abstract)

G. Cabodi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 258

Efficient state assignment framework for asynchronous state graphs (Abstract)

C. Ykman-Couvreur , IMEC, Leuven, Belgium
B. Lin , IMEC, Leuven, Belgium
pp. 692
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin

Adaptive routing in Clos networks (Abstract)

P.A. Franaszek , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
C.J. Georgiou , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Chung-Sheng Li , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 266

Rational clocking [digital systems design] (Abstract)

L.F.G. Sarmenta , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
G.A. Pratt , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
S.A. Ward , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 271

A prototype router for the massively parallel computer RWC-1 (Abstract)

T. Yokota , Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
H. Matsuoka , Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
K. Okamoto , Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
H. Hirono , Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
A. Hori , Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
S. Sakai , Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
pp. 279
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux

Distributed automatic test pattern generation with a parallel FAN algorithm (Abstract)

S. Radtke , IBM Germany, Hannover, Germany
J. Bargfrede , IBM Germany, Hannover, Germany
W. Anheier , IBM Germany, Hannover, Germany
pp. 698

Concurrent automatic test pattern generation algorithm for combinational circuits (Abstract)

A.F. Yousif , Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Jun Gu , Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
pp. 286

Test generation for multiple state-table faults in finite-state machines (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 292
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments

Pollution control caching (Abstract)

S.J. Walsh , IBM Corp., Research Triangle Park, NC, USA
J.A. Board , IBM Corp., Research Triangle Park, NC, USA
pp. 300

Caching processor general registers (Abstract)

R. Yung , Sun Microsystems Labs, Mountain View, CA, USA
N.C. Wilhelm , Sun Microsystems Labs, Mountain View, CA, USA
pp. 307

A dynamic cache sub-block design to reduce false sharing (Abstract)

M. Kadiyala , Nat. Instrum. Corp., Austin, TX, USA
L.N. Bhuyan , Nat. Instrum. Corp., Austin, TX, USA
pp. 313
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin

A programmable routing controller for flexible communications in point-to-point networks (Abstract)

S.W. Daniel , Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
J.L. Rexford , Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
J.W. Dolter , Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
K.G. Shin , Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 320

POM: a processor model for image processing (Abstract)

J.-P. Theis , Applied Microelectron. Lab., Public Res Centre Henri Tudor, Luxembourg City, Luxembourg
L. Thiele , Applied Microelectron. Lab., Public Res Centre Henri Tudor, Luxembourg City, Luxembourg
pp. 326

A case study in low-power system-level design (Abstract)

A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 332
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer

A novel architecture for an ATM switch (Abstract)

Jin Li , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Chuan-Lin Wu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 340

Designing fibre channel fabrics (Abstract)

L. Cherkasova , Hewlett-Packard Co., Palo Alto, CA, USA
V. Kotov , Hewlett-Packard Co., Palo Alto, CA, USA
T. Rokicki , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 346

Architecture and design of a 40 gigabit per second ATM switch (Abstract)

S.E. Butner , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
D.A. Skirmont , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 352
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.

Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits (Abstract)

F. Beeftink , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. Van Genderen , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
N.P. Van Der Meijs , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 360

An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering (Abstract)

Jin-Tai Yan , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 366

FPGA global routing based on a new congestion metric (Abstract)

Yao-Wen Chang , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
C.K. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 372
Session 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah

Asynchronous 2-D discrete cosine transform core processor (Abstract)

B. Stott , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
D. Johnson , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
V. Akella , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
pp. 380

A self-timed redundant-binary number to binary number converter for digital arithmetic processors (Abstract)

Chin-Long Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Haiyan Wang , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Cheng-Ping Wang , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 386
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx

Design and analysis of FPGA/FPIC switch modules (Abstract)

Yao-Wen Chang , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
C.K. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 394

Simultaneous area and delay minimum K-LUT mapping for K-exact networks (Abstract)

S. Thakur , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 402

DART: delay and routability driven technology mapping for LUT based FPGAs (Abstract)

Aigo Lu , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
E. Dagless , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
J. Saul , Dept. of Electr. & Electron. Eng., Bristol Univ., UK
pp. 409

Logic synthesis for a single large look-up table (Abstract)

R. Murgai , Fujitsu Labs of America Inc., San Jose, CA, USA
M. Fujita , Fujitsu Labs of America Inc., San Jose, CA, USA
F. Hirose , Fujitsu Labs of America Inc., San Jose, CA, USA
pp. 415
Session 3.1.1: Design & Test Plenary, Chair: Alexander Albicki, University of Rochester

Testing-what's missing? An incomplete list of challenges (Abstract)

S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 426
Session 3.1.2: CAD Plenary, Chair: Luc Claesen, IMEC

Toward integrated system design: a global perspective (Abstract)

B.J. Hosticka , Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisberg, Germany
pp. 428
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG

Analysis of conditional resource sharing using a guard-based control representation (Abstract)

I.P. Radivojevic , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 434

Multi-dimensional interleaving for time-and-memory design optimization (Abstract)

N.L. Passes , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E.H.-M. Sha , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
Liang-Fang Chao , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 440

High level profiling based low power synthesis technique (Abstract)

S. Katkoori , Dept. of ECE&CS, Cincinnati Univ., OH, USA
N. Kumar , Dept. of ECE&CS, Cincinnati Univ., OH, USA
R. Vemuri , Dept. of ECE&CS, Cincinnati Univ., OH, USA
pp. 446
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard

Control unit synthesis targeting low-power processors (Abstract)

Chuan-Yu Wang , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 454

Low power data format converter design using semi-static register allocation (Abstract)

K. Srivatsan , Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
C. Chakrabarti , Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
L. Lucke , Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
pp. 460

A 13.3ns double-precision floating-point ALU and multiplier (Abstract)

H. Yamada , Res. Lab., Hitachi Ltd., Kanagawa, Japan
T. Hotta , Res. Lab., Hitachi Ltd., Kanagawa, Japan
T. Nishiyama , Res. Lab., Hitachi Ltd., Kanagawa, Japan
F. Murabayashi , Res. Lab., Hitachi Ltd., Kanagawa, Japan
T. Yamauchi , Res. Lab., Hitachi Ltd., Kanagawa, Japan
H. Sawamoto , Res. Lab., Hitachi Ltd., Kanagawa, Japan
pp. 466
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida

A floating point radix 2 shared division/square root chip (Abstract)

H.R. Srinivas , AT&T Bell Labs., Allentown, PA, USA
K.K. Parhi , AT&T Bell Labs., Allentown, PA, USA
pp. 472

High-radix SRT division with speculation of quotient digits (Abstract)

Tzu-Hsi Pan , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Hyon-Sok Kay , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Youngsun Chun , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Chin-Long Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 479

A coprocessor for accurate and reliable numerical computations (Abstract)

M.J. Schulte , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr. , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 686
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University

Special purpose FPGA for high-speed digital telecommunication systems (Abstract)

A. Tsutsui , NTT Opt. Network Syst. Labs., Kanagawa, Japan
T. Miyazaki , NTT Opt. Network Syst. Labs., Kanagawa, Japan
K. Yamada , NTT Opt. Network Syst. Labs., Kanagawa, Japan
N. Ohta , NTT Opt. Network Syst. Labs., Kanagawa, Japan
pp. 486

VLSI design of densely-connected array processors (Abstract)

E.Y. Chou , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
B.J. Sheu , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
T.H. Wu , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
R.C. Chang , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 492

VLSI issues in memory-system design for video signal processors (Abstract)

S. Dutta , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 498
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center

Write buffer design for cache-coherent shared-memory multiprocessors (Abstract)

F. Mounes-Toussi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
D.J. Lilja , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 506

Reducing data access penalty using intelligent opcode-driven cache prefetching (Abstract)

Chi-Hung Chi , Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Siu-Chung Lau , Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
pp. 512

Interrupt-based hardware support for profiling memory system performance (Abstract)

A. Goldberg , AT&T Bell Labs., Murray Hill, NJ, USA
J. Trotter , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 518
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.

Verification of a subtractive radix-2 square root algorithm and implementation (Abstract)

M. Leeser , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
J. O'Leary , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 526

Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors (Abstract)

Y.V. Hoskote , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
D. Moundanos , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 532

Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification (Abstract)

D.A. Cyrluk , Dept. of Comput. Sci., Stanford Univ., CA, USA
M.K. Srivas , Dept. of Comput. Sci., Stanford Univ., CA, USA
pp. 538
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories

An empirical study of datapath, memory hierarchy, and network in SIMD array architectures (Abstract)

M.C. Herbordt , Dept. of Electr. & Comput. Eng., Houston Univ., TX, USA
C.C. Weems , Dept. of Electr. & Comput. Eng., Houston Univ., TX, USA
pp. 546

Memory organization for video algorithms on programmable signal processors (Abstract)

E. de Greef , VLSI Syst. Design Group, IMEC, Leuven, Belgium
F. Catthoor , VLSI Syst. Design Group, IMEC, Leuven, Belgium
H. De Man , VLSI Syst. Design Group, IMEC, Leuven, Belgium
pp. 552

SSM-MP: more scalability in shared-memory multi-processor (Abstract)

S. Iwasa , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
Shung Ho Shing , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Mogi , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Nozuwe , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Hayashi , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
O. Wakamori , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
T. Ohmizo , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
K. Tanaka , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Sakai , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
M. Saito , Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
pp. 558
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University

Low power and high speed multiplication design through mixed number representations (Abstract)

Menghui Zheng , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 566

Minimal self-correcting shift counters (Abstract)

A.M. Tokarnia , Fac. de Engenharia Eletrica, Univ. Estadual de Campinas, Sao Paulo, Brazil
A.M. Peterson , Fac. de Engenharia Eletrica, Univ. Estadual de Campinas, Sao Paulo, Brazil
pp. 571

Estimation of sequential circuit activity considering spatial and temporal correlations (Abstract)

Tan-Li Chou , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 577
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation

A symbolic-simulation approach to the timing verification of interacting FSMs (Abstract)

A.J. Daga , Interconnectix Inc., Portland, OR, USA
W.P. Birmingham , Interconnectix Inc., Portland, OR, USA
pp. 584

Incremental methods for FSM traversal (Abstract)

G.M. Swamy , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
V. Singhal , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 590

Extraction of finite state machines from transistor netlists by symbolic simulation (Abstract)

M. Pandey , Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Jain , Carnegie Mellon Univ., Pittsburgh, PA, USA
R.E. Bryant , Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Beatty , Carnegie Mellon Univ., Pittsburgh, PA, USA
G. York , Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Jain , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 596

Dynamic minimization of OKFDDs (Abstract)

R. Drechsler , Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker , Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 602
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC

Data parallel fault simulation (Abstract)

M.B. Amin , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 610

A parallel algorithm for fault simulation based on PROOFS (Abstract)

S. Parkes , Sierra Vista Res. Inc., Los Gatos, CA, USA
P. Banerjee , Sierra Vista Res. Inc., Los Gatos, CA, USA
J. Patel , Sierra Vista Res. Inc., Los Gatos, CA, USA
pp. 616

Statistics on concurrent fault and design error simulation (Abstract)

B. Grayson , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
S.A. Shaikh , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
S.A. Szygenda , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 622

A new architectural-level fault simulation using propagation prediction of grouped fault-effects (Abstract)

M.S. Hsiao , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 628
Session 3.4.3: Application-Specific Processors, Chair: Ashwiai Nanda, Texas Instruments

A CMOS wave-pipelined image processor for real-time morphology (Abstract)

R.K. Krishnamurthy , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
R. Sridhar , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 638

An efficient systolic array for the discrete cosine transform based on prime-factor decomposition (Abstract)

Hyesook Lim , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr. , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 644

Systolic algorithms for tree pattern matching (Abstract)

A. Ejnioui , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 650

Smart-pixel array processors based on optimal cellular neural networks for space sensor applications (Abstract)

Wai-Chi Fang , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
B.J. Sheu , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
H. Venus , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
R. Sandau , Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 703
Session 3.4.4: Performance Driven Synthesis, Chair: Andreas Kuehlmann, IBM T.J. Watson Research Center

Logic extraction based on normalized netlengths (Abstract)

H. Vaishnav , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 658

Transformation of min-max optimization to least-square estimation and application to interconnect design optimization (Abstract)

J. Shinn-Hwa Wang , Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
W. Wei-Ming Dai , Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
pp. 664

Simple tree-construction heuristics for the fanout problem (Abstract)

R.J. Carragher , Fujitsu Labs. of America Inc., San Jose, CA, USA
M. Fujita , Fujitsu Labs. of America Inc., San Jose, CA, USA
Chung-Kuan Cheng , Fujitsu Labs. of America Inc., San Jose, CA, USA
pp. 671

Concurrent timing optimization of latch-based digital systems (Abstract)

Hong-Yean Hsieh , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Wentai Liu , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
R.K. Cavin , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
C.T. Gray , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 680

Index of Authors (PDF)

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