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2012 IEEE 30th International Conference on Computer Design (ICCD) (1995)
Austin, Texas
Oct. 2, 1995 to Oct. 4, 1995
ISSN: 1063-6404
ISBN: 0-8186-7165-3
pp: 616
P. Banerjee , Sierra Vista Res. Inc., Los Gatos, CA, USA
S. Parkes , Sierra Vista Res. Inc., Los Gatos, CA, USA
J. Patel , Sierra Vista Res. Inc., Los Gatos, CA, USA
ABSTRACT
Fault simulation for sequential circuits numbers among the highly compute intensive tasks in the integrated circuit design process. In the quest for rapid design turn around, parallelization has been proposed to speed fault simulation. We introduce ProperPROOFS, a parallel extension of the PROOFS fault simulation package. ProperPROOFS exploits parallelism based on fault partitioning, incorporating static and dynamic partitioning schemes and a new asynchronous and distributed method of fault redistribution. We present results for circuits in the ISCAS-89 benchmark set across several parallel architectures. A detailed evaluation of results provides new insight into the use of fault partitioning to parallelize high performance serial fault simulation applications.
INDEX TERMS
circuit analysis computing; fault diagnosis; logic testing; sequential circuits; logic partitioning; parallel algorithms; parallel architectures; parallel algorithm; fault partitioning; dynamic partitioning schemes; sequential circuits; compute intensive task; integrated circuit design process; rapid design turn around; ProperPROOFS; parallel extension; PROOFS fault simulation package; distributed method; fault redistribution; ISCAS-89 benchmark set; parallel architectures; high performance serial fault simulation applications
CITATION
P. Banerjee, S. Parkes, J. Patel, "A parallel algorithm for fault simulation based on PROOFS", 2012 IEEE 30th International Conference on Computer Design (ICCD), vol. 00, no. , pp. 616, 1995, doi:10.1109/ICCD.1995.528932
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