The Community for Technology Leaders
Computer-Aided Design, International Conference on (2011)
San Jose, CA, USA
Nov. 7, 2011 to Nov. 10, 2011
ISBN: 978-1-4577-1399-6
TABLE OF CONTENTS
Papers

Front matter (PDF)

pp. 1-2

Foreword (PDF)

pp. 1

Awards (PDF)

pp. 1

Keynote address: Design of secure systems -- Where are the EDA tools? (PDF)

Georg Sigl , Technische Univ. München and Fraunhofer AISEC
pp. 1

Panels (PDF)

pp. 1

Table of contents (PDF)

pp. 1-12

Author index (PDF)

pp. 1-10

Layout decomposition for triple patterning lithography (Abstract)

Bei Yu , ECE Dept. University of Texas at Austin, Austin, TX USA 78712
Kun Yuan , Cadence Design Systems, Inc., San Jose, CA USA 95134
Boyang Zhang , ECE Dept. University of Texas at Austin, Austin, TX USA 78712
Duo Ding , ECE Dept. University of Texas at Austin, Austin, TX USA 78712
David Z. Pan , ECE Dept. University of Texas at Austin, Austin, TX USA 78712
pp. 1-8

Optimal layout decomposition for double patterning technology (Abstract)

Xiaoping Tang , IBM T.J. Waston Research Center
Minsik Cho , IBM T.J. Watson Research Center
pp. 9-13

A framework for double patterning-enabled design (Abstract)

Rani S. Ghaida , UCLA, Electrical Engineering Dept
Kanak B. Agarwal , IBM Corp., Austin Research Lab
Sani R. Nassif , IBM Corp., Austin Research Lab
Xin Yuan , IBM Corp., San Jose
Lars W. Liebmann , IBM Corp., Semiconductor Research & Development Center
Puneet Gupta , UCLA, Electrical Engineering Dept
pp. 14-20

Unequal-error-protection codes in SRAMs for mobile multimedia applications (Abstract)

Xuebei Yang , Department of Electrical and Computer Engineering, Rice University, Houston
Kartik Mohanram , Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh
pp. 21-27

Detecting stability faults in sub-threshold SRAMs (Abstract)

Chen-Wei Lin , Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan
Hao-Yu Yang , Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan
Chin-Yuan Huang , Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan
Hung-Hsin Chen , Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan
Mango C.-T. Chao , Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan
pp. 28-33

Pseudo-functional testing for small delay defects considering power supply noise effects (Abstract)

Feng Yuan , CUhk REliable Computing Laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Xiao Liu , CUhk REliable Computing Laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable Computing Laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 34-39

A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding (Abstract)

Bruno Zatt , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Karlsruhe, Germany
Muhammad Shafique , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Karlsruhe, Germany
Sergio Bampi , Federal University of Rio Grande do Sul (UFRGS), Informatics Institute/PGMICRO, Porto Alegre, Brazil
Jorg Henkel , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Karlsruhe, Germany
pp. 40-47

Bandwidth-aware reconfigurable cache design with hybrid memory technologies (Abstract)

Jishen Zhao , Computer Science and Engineering Department, Pennsylvania State University
Cong Xu , Computer Science and Engineering Department, Pennsylvania State University
Yuan Xie , Computer Science and Engineering Department, Pennsylvania State University
pp. 48-55

Feedback control based cache reliability enhancement for emerging multicores (Abstract)

Hui Zhao , Department of Computer Science and Engineering, The Pennsylvania State University
Akbar Sharifi , Department of Computer Science and Engineering, The Pennsylvania State University
Shekhar Srikantaiah , Department of Computer Science and Engineering, The Pennsylvania State University
Mahmut Kandemir , Department of Computer Science and Engineering, The Pennsylvania State University
pp. 56-62

GPU programming for EDA with OpenCL (Abstract)

Rasit O. Topaloglu , GLOBALFOUNDRIES, 840 N McCarthy Blvd, Milpitas CA 95035
Benedict Gaster , Advanced Micro Devices, 1 AMD Pl, Sunnyvale CA 94085
pp. 63-66

A SimPLR method for routability-driven placement (Abstract)

Myung-Chul Kim , University of Michigan, Department of EECS, 2260 Hayward St, Ann Arbor, MI 48109-2121
Jin Hu , University of Michigan, Department of EECS, 2260 Hayward St, Ann Arbor, MI 48109-2121
Dong-Jin Lee , University of Michigan, Department of EECS, 2260 Hayward St, Ann Arbor, MI 48109-2121
Igor L. Markov , University of Michigan, Department of EECS, 2260 Hayward St, Ann Arbor, MI 48109-2121
pp. 67-73

Ripple: An effective routability-driven placer by iterative cell movement (Abstract)

Xu He , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Tao Huang , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Linfu Xiao , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Haitong Tian , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Guxin Cui , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Evangeline F.Y. Young , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 74-79

Routability-driven analytical placement for mixed-size circuit designs (Abstract)

Meng-Kai Hsu , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Sheng Chou , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Tzu-Hen Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 80-84

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs (Abstract)

Yi-Lin Chuang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Hong-Ting Lin , Dept. of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Tsung-Yi Ho , Dept. of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Diana Marculescu , Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 85-90

Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories (Abstract)

Dimitri De Jonghe , K.U. Leuven, ESAT-MICAS, B-3001 Heverlee, Belgium
Georges Gielen , K.U. Leuven, ESAT-MICAS, B-3001 Heverlee, Belgium
pp. 91-94

Optimal statistical chip disposition (Abstract)

Vladimir Zolotov , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
pp. 95-102

Temperature aware statistical static timing analysis (Abstract)

Artem Rogachev , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
Lu Wan , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
Deming Chen , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
pp. 103-110

Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers (Abstract)

Bing Li , Ulf Schlichtmann Institute for Electronic Design Automation, Technische Universitaet Muenchen, Germany
Ning Chen , Ulf Schlichtmann Institute for Electronic Design Automation, Technische Universitaet Muenchen, Germany
pp. 111-117

Improving shared cache behavior of multithreaded object-oriented applications in multicores (Abstract)

Mahmut Kandemir , Pennsylvania State University, University Park, PA
Shekhar Srikantaiah , Pennsylvania State University, University Park, PA
Seung Woo Son , Argonne National Lab, Argonne, IL
pp. 118-125

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique (Abstract)

Mohammad Shihabul Haque , School of Computer Science and Engineering, University of New South Wales, Australia
Jorgen Peddersen , School of Computer Science and Engineering, University of New South Wales, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Australia
pp. 126-133

Cooperative parallelization (Abstract)

Praveen Yedlapalli , The Pennsylvania State University
Emre Kultursay , The Pennsylvania State University
Mahmut T. Kandemir , The Pennsylvania State University
pp. 134-141

Optimizing data locality using array tiling (Abstract)

Wei Ding , The Pennsylvania State University, University Park, PA 16802, U.S.A
Yuanrui Zhang , The Pennsylvania State University, University Park, PA 16802, U.S.A
Jun Liu , The Pennsylvania State University, University Park, PA 16802, U.S.A
Mahmut Kandemir , The Pennsylvania State University, University Park, PA 16802, U.S.A
pp. 142-149

Assuring application-level correctness against soft errors (Abstract)

Jason Cong , Department of Computer Science, University of California, Los Angeles, CA 90024 USA
Karthik Gururaj , Department of Computer Science, University of California, Los Angeles, CA 90024 USA
pp. 150-157

The role of EDA in digital print automation and infrastructure optimization (Abstract)

Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC
Gary Dispoto , Print Content Delivery Laboratory, Hewlett-Packard Laboratories, Palo Alto, CA
Rick Bellamy , RPI, Seattle, WA
Jun Zeng , Print Content Delivery Laboratory, Hewlett-Packard Laboratories Palo Alto, CA
pp. 158-161

Toward efficient spatial variation decomposition via sparse regression (Abstract)

Wangyang Zhang , Carnegie Mellon University, Pittsburgh, PA 15213
Karthik Balakrishnan , Massachusetts Institute of Technology, Cambridge, MA 02139
Xin Li , Carnegie Mellon University, Pittsburgh, PA 15213
Duane Boning , Massachusetts Institute of Technology, Cambridge, MA 02139
Rob Rutenbar , University of Illinois at Urbana-Champaign, Urbana, IL 61801
pp. 162-169

REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations (Abstract)

Charles Lamech , ECE Dept., Univ. of New Mexico
James Aarestad , ECE Dept., Univ. of New Mexico
Jim Plusquellic , ECE Dept., Univ. of New Mexico
Reza Rad , ECE Dept., Univ. of New Mexico
Kanak Agarwal , IBM Austin Research Laboratory
pp. 170-177

Accelerating aerial image simulation with GPU (Abstract)

Hongbo Zhang , Dept. of ECE, University of Illinois at Urbana-Champaign, Urbana, Illinois, USA
Tan Yan , Synopsys, Inc., Mountain View, California, USA
Martin D. F. Wong , Dept. of ECE, University of Illinois at Urbana-Champaign, Urbana, Illinois, USA
Sanjay J. Patel , Dept. of ECE, University of Illinois at Urbana-Champaign, Urbana, Illinois, USA
pp. 178-184

Combined loop transformation and hierarchy allocation for data reuse optimization (Abstract)

Jason Cong , Computer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USA
Peng Zhang , Computer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USA
Yi Zou , Computer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USA
pp. 185-192

High-level synthesis with distributed controller for fast timing closure (Abstract)

Seokhyun Lee , Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea
Kiyoung Choi , Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea
pp. 193-199

Synthesis of parallel binary machines (Abstract)

Elena Dubrova , Royal Institute of Technology, IMIT/KTH, 164 40 Kista, Sweden
pp. 200-206

Chemical-mechanical polishing aware application-specific 3D NoC design (Abstract)

Wooyoung Jang , SoC Platform Development Team, Samsung Electronics, Yongin-City, South Korea
Ou He , IBM System & Technology Group, Beijing, China
Jae-Seok Yang , CAE Team, Samsung Electronics, Hwaseung-City, South Korea
David Z. Pan , Department of Electrical and Computer Engineering, the University of Texas at Austin, Austin, USA
pp. 207-212

Application-aware deadlock-free oblivious routing based on extended turn-model (Abstract)

Ali Shafiee , CE Department, Sharif University of Technology, Tehran, Iran
Mahdy Zolghadr , CE Department, Sharif University of Technology, Tehran, Iran
Mohammad Arjomand , CE Department, Sharif University of Technology, Tehran, Iran
Hamid Sarbazi-azad , CE Department, Sharif University of Technology, Tehran, Iran
pp. 213-218

Co-design of channel buffers and crossbar organizations in NoCs architectures (Abstract)

Avinash Kodi , Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701
Randy Morris , Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701
Dominic DiTomaso , Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701
Ashwini Sarathy , Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721
Ahmed Louri , Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721
pp. 219-226

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated (Abstract)

Hai Wei , Department of Electrical Engineering, Stanford University, CA
Jie Zhang , Department of Electrical Engineering, Stanford University, CA
Lan Wei , Microsystems Technology Laboratories, Massachusetts Institute of Technology, MA
Nishant Patil , Department of Electrical Engineering, Stanford University, CA
Albert Lin , Department of Electrical Engineering, Stanford University, CA
Max M. Shulaker , Department of Electrical Engineering, Stanford University, CA
Hong-Yu Chen , Department of Electrical Engineering, Stanford University, CA
H.-S. Philip Wong , Department of Electrical Engineering, Stanford University, CA
Subhasish Mitra , Department of Electrical Engineering, Stanford University, CA
pp. 227-230

Alternative design methodologies for the next generation logic switch (Abstract)

Davide Sacchetto , Integrated System Laboratory (LSI), Ecole Polytechnique Fédérale de Lausanne, Switzerland
Michele De Marchi , Integrated System Laboratory (LSI), Ecole Polytechnique Fédérale de Lausanne, Switzerland
Giovanni De Micheli , Integrated System Laboratory (LSI), Ecole Polytechnique Fédérale de Lausanne, Switzerland
Yusuf Leblebici , Integrated System Laboratory (LSI), Ecole Polytechnique Fédérale de Lausanne, Switzerland
pp. 231-234

Progress and outlook for STT-MRAM (Abstract)

Yiming Huai , Avalanche Technology, 48371 Fremont Blvd., Suite 101, Fremont, CA 94538
Yuchen Zhou , Avalanche Technology, 48371 Fremont Blvd., Suite 101, Fremont, CA 94538
Ioan Tudosa , Avalanche Technology, 48371 Fremont Blvd., Suite 101, Fremont, CA 94538
Roger Malmhall , Avalanche Technology, 48371 Fremont Blvd., Suite 101, Fremont, CA 94538
Rajiv Ranjan , Avalanche Technology, 48371 Fremont Blvd., Suite 101, Fremont, CA 94538
Jing Zhang , Avalanche Technology, 48371 Fremont Blvd., Suite 101, Fremont, CA 94538
pp. 235

Universal statistical cure for predicting memory loss (Abstract)

Rajiv Joshi , IBM T.J. Watson Lab, Yorktown Heights, NY 10598, USA
Rouwaida Kanj , IBM Austin Research Labs, Austin TX, 78681
Peiyuan Wang , Department of ECE, University of Pittsburgh, Pittsburgh, PA
Hai (Helen) Li , Department of ECE, Polytechnic Institute of NYU, Brooklyn, NY 11201, NYU
pp. 236-239

Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits (Abstract)

Guillaume Prenat , Spintec, CEA/INAC, 17, rue des Martyrs, 38054, Grenoble, France
Bernard Dieny , Spintec, CEA/INAC, 17, rue des Martyrs, 38054, Grenoble, France
Jean-Pierre Nozieres , Spintec, CEA/INAC, 17, rue des Martyrs, 38054, Grenoble, France
Gregory DiPendina , CMP, CNRS 46, avenue Felix Viallet 38031, Grenoble, France
Kholdoun Torki , CMP, CNRS 46, avenue Felix Viallet 38031, Grenoble, France
pp. 240-245

Progress in CMOS-memristor integration (Abstract)

Gilberto Medeiros-Ribeiro , Nanoelectronics Research Group, Hewlett-Packard Laboratories, Palo Alto, USA
Janice H. Nickel , Nanoelectronics Research Group, Hewlett-Packard Laboratories, Palo Alto, USA
J. Joshua Yang , Nanoelectronics Research Group, Hewlett-Packard Laboratories, Palo Alto, USA
pp. 246-249

MGR: Multi-level global router (Abstract)

Yue Xu , Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011-3060, USA
Chris Chu , Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011-3060, USA
pp. 250-255

Congestion analysis for global routing via integer programming (Abstract)

Hamid Shojaei , Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA
Azadeh Davoodi , Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA
Jeffrey T. Linderoth , Department of Industrial and Systems Engineering, University of Wisconsin at Madison, USA
pp. 256-262

High-quality global routing for multiple dynamic supply voltage designs (Abstract)

Wen-Hao Liu , Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan
Yih-Lang Li , Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan
Kai-Yuan Chao , Intel Architecture Group, Intel Corporation, Hillsboro, OR
pp. 263-269

The future of clock network synthesis (Abstract)

Cliff Sze , IBM Research, Austin, Texas, USA
pp. 270

Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus (Abstract)

Joseph Kozhaya , IBM EDA, 3039 E. Cornwallis Rd RTP, NC 27709
Phillip Restle , IBM Research 1101 Kitchawan Rd Yorktown Heights, NY 10598
Haifeng Qian , IBM Research 1101 Kitchawan Rd Yorktown Heights, NY 10598
pp. 271-275

Clocking design automation in Intel's Core i7 and future designs (Abstract)

Ali M. El-Husseini , Intel Corporation, Jones Farm Campus, 2111 NW 25th Avenue, Hillsboro, OR 97124
Matthew Morrise , Intel Corporation, Jones Farm Campus, 2111 NW 25th Avenue, Hillsboro, OR 97124
pp. 276-278

Algorithmic tuning of clock trees and derived non-tree structures (Abstract)

Igor L. Markov , University of Michigan, 2260 Hayward St., Ann Arbor, MI 48109-2121
Dong-Jin Lee , University of Michigan, 2260 Hayward St., Ann Arbor, MI 48109-2121
pp. 279-282

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing (Abstract)

Yen-Hung Lin , Department of Compuer Science, National Chiao Tung University Hsinchu Taiwan
Yong-Chan Ban , Department of Electrical and Computer Engineering, University of Texas at Austin, Texas, USA
David Z. Pan , Department of Electrical and Computer Engineering, University of Texas at Austin, Texas, USA
Yih-Lang Li , Department of Compuer Science, National Chiao Tung University Hsinchu Taiwan
pp. 283-289

A jumper insertion algorithm under antenna ratio and timing constraints (Abstract)

Xin Gao , Department of Electrical Engineering, University of Hawaii at Manoa, Honolulu 96822, USA
Luca Macchiarulo , Department of Electrical Engineering, University of Hawaii at Manoa, Honolulu 96822, USA
pp. 290-297

Exploring high throughput computing paradigm for global routing (Abstract)

Yiding Han , Electrical and Computer Engineering, Utah State University
Dean Michael Ancajas , Electrical and Computer Engineering, Utah State University
Koushik Chakraborty , Electrical and Computer Engineering, Utah State University
Sanghamitra Roy , Electrical and Computer Engineering, Utah State University
pp. 298-305

Escape routing for staggered-pin-array PCBs (Abstract)

Yuan-Kai Ho , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Hsu-Chieh Lee , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 306-309

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning (Abstract)

Matthew Grange , Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster LA1 4YR, United Kingdom
Axel Jantsch , Dept. of Electronic, Communication, and Software Systems, Royal Institute of Technology (KTH), Forum 120, SE-164 40 Kista, Sweden
Roshan Weerasekera , Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster LA1 4YR, United Kingdom
Dinesh Pamunuwa , Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster LA1 4YR, United Kingdom
pp. 310-317

The STeTSiMS STT-RAM simulation and modeling system (Abstract)

Clinton W. Smullen , Department of Computer Science
Anurag Nigam , Department of Electrical and Computer Engineering, University of Virginia
Sudhanva Gurumurthi , Department of Computer Science
Mircea R. Stan , Department of Electrical and Computer Engineering, University of Virginia
pp. 318-325

Massively parallel programming models used as hardware description languages: The OpenCL case (Abstract)

Muhsen Owaida , Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece
Nikolaos Bellas , Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece
Christos D. Antonopoulos , Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece
Konstantis Daloukas , Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece
Charalambos Antoniadis , Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece
pp. 326-333

Neuromorphic modeling abstractions and simulation of large-scale cortical networks (Abstract)

Jeffrey L. Krichmar , Department of Cognitive Sciences
Nikil Dutt , Department of Computer Science, University of California, Irvine, Irvine, CA, USA
Jayram M. Nageswaran , Brain Corporation, San Diego, CA, USA
Micah Richert , Brain Corporation, San Diego, CA, USA
pp. 334-338

A framework for accelerating neuromorphic-vision algorithms on FPGAs (Abstract)

M. DeBole , Dept. of CSE, The Pennsylvania State University, University Park, PA 16802, USA
A. Al Maashri , Dept. of CSE, The Pennsylvania State University, University Park, PA 16802, USA
M. Cotter , Dept. of CSE, The Pennsylvania State University, University Park, PA 16802, USA
C-L. Yu , School of ECEE, Arizona State University Tempe, AZ 85287, USA
C. Chakrabarti , School of ECEE, Arizona State University Tempe, AZ 85287, USA
V. Narayanan , School of ECEE, Arizona State University Tempe, AZ 85287, USA
pp. 810-813

A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis (Abstract)

Yu Wang , Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University
Mo Xu , Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University
Ling Ren , Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University
Xiaorui Zhang , Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University
Di Wu , Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University
Yong He , State Key Laboratory of Cognitive Neuroscience and Learning, Beijing Normal University
Ningyi Xu , Hardware Computing Group, Microsoft Research Asia
Huazhong Yang , Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology Tsinghua University
pp. 339-344

Fast statistical model of TiO (Abstract)

Miao Hu , Dept. of ECE, Polytechnic Institute of NYU, Brooklyn, NY, USA
Hai Li , Dept. of ECE, Polytechnic Institute of NYU, Brooklyn, NY, USA
Robinson E. Pino , Air Force Research Laboratory, Advanced Computing, Rome, NY, USA
pp. 345-352

Accelerated statistical simulation via on-demand Hermite spline interpolations (Abstract)

Rouwaida Kanj , IBM Austin Research Labs, Austin TX
Tong Li , IBM Systems and Technology Group, Austin TX
Rajiv Joshi , IBM TJ Watson Research Labs, Yorktown Heights NY
Kanak Agarwal , IBM Austin Research Labs, Austin TX
Ali Sadigh , IBM Systems and Technology Group, Austin TX
David Winston , IBM Systems and Technology Group, Austin TX
Sani Nassif , IBM Austin Research Labs, Austin TX
pp. 353-360

Structure preserving reduced-order modeling of linear periodic time-varying systems (Abstract)

Ting Mei , Sandia National Laboratories, Albuquerque, NM, USA
Heidi Thornquist , Sandia National Laboratories, Albuquerque, NM, USA
Eric Keiter , Sandia National Laboratories, Albuquerque, NM, USA
Scott Hutchinson , Sandia National Laboratories, Albuquerque, NM, USA
pp. 361-366

ModSpec: An open, flexible specification framework for multi-domain device modelling (Abstract)

David Amsallem , University of California, Berkeley
Jaijeet Roychowdhury , University of California, Berkeley
pp. 367-374

Delay optimization using SOP balancing (Abstract)

Alan Mishchenko , Department of EECS, University of California, Berkeley
Robert Brayton , Department of EECS, University of California, Berkeley
Stephen Jang , Agate Logic Inc
Victor Kravets , IBM Corporation
pp. 375-382

Match and replace -- A functional ECO engine for multi-error circuit rectification (Abstract)

Shao-Lun Huang , Department of Electrical Engineering
Wei-Hsun Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
Chung-Yang (Ric) Huang , Department of Electrical Engineering
pp. 383-388

Towards completely automatic decoder synthesis (Abstract)

Hsiou-Yuan Liu , Department of Electrical Engineering
Yen-Cheng Chou , Department of Electrical Engineering
Chen-Hsuan Lin , Graduate Institute of Electronics Engineering National Taiwan University, Taipei 10617, Taiwan
Jie-Hong R. Jiang , Department of Electrical Engineering
pp. 389-395

On rewiring and simplification for canonicity in threshold logic circuits (Abstract)

Pin-Yi Kuo , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Chun-Yao Wang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Ching-Yi Huang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
pp. 396-403

Inferring assertion for complementary synthesis (Abstract)

ShengYu Shen , School of Computer Science, National University of Defense Technology, 410073, DeYa Avenue, ChangSha, China
Ying Qin , School of Computer Science, National University of Defense Technology, 410073, DeYa Avenue, ChangSha, China
JianMin Zhang , School of Computer Science, National University of Defense Technology, 410073, DeYa Avenue, ChangSha, China
pp. 404-411

Statistical aging analysis with process variation consideration (Abstract)

Sangwoo Han , Department of Computer Science Engineering, Sogang University, Seoul, Rep. of Korea
Joohee Choung , Department of Computer Science Engineering, Sogang University, Seoul, Rep. of Korea
Byung-Su Kim , Samsung Electronics Co. Ltd., Seoul, Rep. of Korea
Bong Hyun Lee , Samsung Electronics Co. Ltd., Seoul, Rep. of Korea
Hungbok Choi , Samsung Electronics Co. Ltd., Seoul, Rep. of Korea
Juho Kim , Department of Computer Science Engineering, Sogang University, Seoul, Rep. of Korea
pp. 412-419

A new method for multiparameter robust stability distribution analysis of linear analog circuits (Abstract)

Changhao Yan , State Key Lab. of ASIC & System, Fudan Univ., Shanghai, China
Sheng-Guo Wang , Dept. of ET / SIS, Univ. of North Carolina at Charlotte, Charlotte, USA
Xuan Zeng , State Key Lab. of ASIC & System, Fudan Univ., Shanghai, China
pp. 420-427

Failure diagnosis of asymmetric aging under NBTI (Abstract)

Jyothi Bhaskarr Velamala , School of ECEE, Arizona State University, Tempe, AZ 85287
Venkatesa Ravi , School of ECEE, Arizona State University, Tempe, AZ 85287
Yu Cao , School of ECEE, Arizona State University, Tempe, AZ 85287
pp. 428-433

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation (Abstract)

Zahra Lak , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada
pp. 434-441

Online clock skew tuning for timing speculation (Abstract)

Rong Ye , CUhk REliable Computing Laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Feng Yuan , CUhk REliable Computing Laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences
pp. 442-447

Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips (Abstract)

Tsung-Wei Huang , Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Tsung-Yi Ho , Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC
pp. 448-455

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously (Abstract)

Yehua Su , ECE Department, University of Illinois at Chicago, IL 60607, USA
Wenjing Rao , ECE Department, University of Illinois at Chicago, IL 60607, USA
pp. 456-462

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems (Abstract)

Cong Xu , Department of Computer Science and Engineering, Pennsylvania State University
Dimin Niu , Department of Computer Science and Engineering, Pennsylvania State University
Xiaochun Zhu , Department of Computer Science and Engineering, Pennsylvania State University
Seung H. Kang , Department of Computer Science and Engineering, Pennsylvania State University
Matt Nowak , Department of Computer Science and Engineering, Pennsylvania State University
Yuan Xie , Department of Computer Science and Engineering, Pennsylvania State University
pp. 463-470

STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view (Abstract)

Yaojun Zhang , Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh PA 15213 USA
Xiaobin Wang , Seagate Technology, Bloomington, MN 55435 USA
Yiran Chen , Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh PA 15213 USA
pp. 471-477

2011 TAU power grid simulation contest: Benchmark suite and results (Abstract)

Zhuo Li , IBM Austin Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Raju Balasubramanian , IBM Systems & Technology Group, 11400 Burnet Road, Austin, TX 78758
Frank Liu , IBM Austin Research Laboratory, 11501 Burnet Road, Austin, TX 78758
Sani Nassif , IBM Austin Research Laboratory, 11501 Burnet Road, Austin, TX 78758
pp. 478-481

PowerRush: A linear simulator for power grid (Abstract)

Jianlei Yang , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Zuowei Li , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Yici Cai , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Qiang Zhou , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
pp. 482-487

Fast static analysis of power grids: Algorithms and implementations (Abstract)

Zhiyu Zeng , Department of ECE, Texas A&M University, College Station, TX, 77843, USA
Tong Xu , Department of ECE, Texas A&M University, College Station, TX, 77843, USA
Zhuo Feng , Department of ECE, Michigan Technological University, Houghton, MI, 49931, USA
Peng Li , Department of ECE, Texas A&M University, College Station, TX, 77843, USA
pp. 488-493

On the preconditioner of conjugate gradient method -- A power grid simulation perspective (Abstract)

Chung-Han Chou , Computer Science Department, National Tsing Hua University
Nien-Yu Tsai , Computer Science Department, National Tsing Hua University
Hao Yu , Computer Science Department, National Tsing Hua University
Che-Rung Lee , Computer Science Department, National Tsing Hua University
Yiyu Shi , ECE Department, Missouri University of Science and Technology
Shih-Chieh Chang , Computer Science Department, National Tsing Hua University
pp. 494-497

PTrace: Derivative-free local tracing of bicriterial design tradeoffs (Abstract)

Amith Singhee , IBM T. J. Watson Research Center, Yorktown Heights, NY USA
pp. 498-502

A methodology for local resonant clock synthesis using LC-assisted local clock buffers (Abstract)

Walter J. Condley , Department of Computer Engineering, University of California Santa Cruz, Santa Cruz, CA 95064
Xuchu Hu , Department of Computer Engineering, University of California Santa Cruz, Santa Cruz, CA 95064
Matthew R. Guthaus , Department of Computer Engineering, University of California Santa Cruz, Santa Cruz, CA 95064
pp. 503-506

A corner stitching compliant B (Abstract)

Hui-Fang Tsao , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Pang-Yen Chou , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Shih-Lun Huang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Mark Po-Hung Lin , Department of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan
Duan-Ping Chen , Lattice Semiconductor Corp., San Jose, CA, USA
Dick Liu , Synopsys Inc., Mountain View, CA, USA
pp. 507-511

Heterogeneous B (Abstract)

Pang-Yen Chou , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Hung-Chih Ou , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 512-516

Fast analog layout prototyping for nanometer design migration (Abstract)

Yi-Peng Weng , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Hung-Ming Chen , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Tung-Chieh Chen , Physical Design Group, Springsoft, Inc., Hsinchu, Taiwan
Po-Cheng Pan , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Chien-Hung Chen , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Wei-Zen Chen , Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
pp. 517-522

Model order reduction of fully parameterized systems by recursive least square optimization (Abstract)

Zheng Zhang , Research Lab of Electronics, Massachusetts Institute of Technology
Ibrahim M. Elfadel , Masdar Institute of Science and Technology, United Arab Emirates
Luca Daniel , Research Lab of Electronics, Massachusetts Institute of Technology
pp. 523-530

Fast poisson solver preconditioned method for robust power grid analysis (Abstract)

Jianlei Yang , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Yici Cai , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Qiang Zhou , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Jin Shi , Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, China
pp. 531-536

Modeling and estimation of power supply noise using linear programming (Abstract)

Farshad Firouzi , Karlsruhe Institute of Technology, Karlsruhe, Germany
Saman Kiamehr , Karlsruhe Institute of Technology, Karlsruhe, Germany
Mehdi B. Tahoori , Karlsruhe Institute of Technology, Karlsruhe, Germany
pp. 537-542

Power grid analysis with hierarchical support graphs (Abstract)

Xueqian Zhao , Department of Electrical and Computer Engineering Michigan Technological University, Houghton, MI, 49931
Jia Wang , Department of Electrical and Computer Engineering Michigan Technological University, Houghton, MI, 49931
Zhuo Feng , Department of Electrical and Computer Engineering Michigan Technological University, Houghton, MI, 49931
Shiyan Hu , Department of Electrical and Computer Engineering Michigan Technological University, Houghton, MI, 49931
pp. 543-547

Vectorless verification of RLC power grids with transient current constraints (Abstract)

Xuanxing Xiong , Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL 60616, USA
Jia Wang , Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL 60616, USA
pp. 548-554

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs (Abstract)

Mohit Pathak , Department of ECE, Georgia Institute of Technology, Atlanta, GA 30332, U.S.A.
Jiwoo Pak , Department of ECE, The University of Texas at Austin, Austin, TX 78712, U.S.A.
David Z. Pan , Department of ECE, The University of Texas at Austin, Austin, TX 78712, U.S.A.
Sung Kyu Lim , Department of ECE, Georgia Institute of Technology, Atlanta, GA 30332, U.S.A.
pp. 555-562

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC (Abstract)

Moongon Jung , School of ECE, Georgia Institute of Technology, Atlanta, GA, USA
Xi Liu , School of ME, Georgia Institute of Technology, Atlanta, GA, USA
Suresh K. Sitaraman , School of ME, Georgia Institute of Technology, Atlanta, GA, USA
David Z. Pan , Department of ECE, University of Texas at Austin, Austin, TX, USA
Sung Kyu Lim , School of ECE, Georgia Institute of Technology, Atlanta, GA, USA
pp. 563-570

Variation-aware electromigration analysis of power/ground networks (Abstract)

Di-an Li , Dept. of Electrical & Computer Engineering, University of California, Santa Barbara, CA, USA
Malgorzata Marek-Sadowska , Dept. of Electrical & Computer Engineering, University of California, Santa Barbara, CA, USA
pp. 571-576

Low-power multiple-bit upset tolerant memory optimization (Abstract)

Seokjoong Kim , Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064
Matthew R. Guthaus , Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064
pp. 577-581

Mitigating FPGA interconnect soft errors by in-place LUT inversion (Abstract)

Naifeng Jing , School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China
Ju-Yueh Lee , Electrical Engineering Department, University of California, Los Angeles, USA
Weifeng He , School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China
Zhigang Mao , School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China
Lei He , Electrical Engineering Department, University of California, Los Angeles, USA
pp. 582-586

Debugging with dominance: On-the-fly RTL debug solution implications (Abstract)

Hratch Mangassarian , University of Toronto, ECE Department, Toronto, ON M5S 3G4
Andreas Veneris , University of Toronto, ECE Department, Toronto, ON M5S 3G4
Duncan Exon Smith , Vennsa Technologies, Inc., Toronto, ON, M5V 3B1
Sean Safarpour , Vennsa Technologies, Inc., Toronto, ON, M5V 3B1
pp. 587-594

Simulation-based signal selection for state restoration in silicon debug (Abstract)

Debapriya Chatterjee , Department of Computer Science and Engineering, University of Michigan
Calvin McCarter , Department of Computer Science and Engineering, University of Michigan
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan
pp. 595-601

Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques (Abstract)

Bo-Han Wu , Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University
Chun-Ju Yang , Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University
Chia-Cheng Tso , Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University
Chung-Yang (Ric) Huang , Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University
pp. 602-607

Identifying the optimal energy-efficient operating points of parallel workloads (Abstract)

Ryan Cochran , School of Engineering, Brown University, Providence, RI 02912
Can Hankendi , ECE Department Boston University, Boston, MA 02215
Ayse Coskun , ECE Department, Boston University, Boston, MA 02215
Sherief Reda , School of Engineering, Brown University Providence, RI 02912
pp. 608-615

System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia (Abstract)

Haris Javaid , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Muhammad Shafique , Chair for Embedded Systems, Karlsruhe Institute of Technology, Karlsruhe, Germany
Jorg Henkel , Chair for Embedded Systems, Karlsruhe Institute of Technology, Karlsruhe, Germany
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
pp. 616-623

Balanced reconfiguration of storage banks in a hybrid electrical energy storage system (Abstract)

Younghyun Kim , Seoul National University, Korea
Sangyoung Park , Seoul National University, Korea
Yanzhi Wang , University of Southern California, CA, USA
Qing Xie , University of Southern California, CA, USA
Naehyuck Chang , Seoul National University, Korea
Massimo Poncino , Politecnico di Torino, Italy
Massoud Pedram , University of Southern California, CA, USA
pp. 624-631

Multilevel tree fusion for robust clock networks (Abstract)

Dong-Jin Lee , University of Michigan, 2260 Hayward St., Ann Arbor, MI 48109-2121
Igor L. Markov , University of Michigan, 2260 Hayward St., Ann Arbor, MI 48109-2121
pp. 632-639

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power (Abstract)

Seungwhun Paik , Dept. of Electrical, Engineering, KAIST, Daejeon 305-701, Korea
Gi-Joon Nam , IBM Austin Research, Laboratory, Austin, Texas
Youngsoo Shin , Dept. of Electrical, Engineering, KAIST, Daejeon 305 - 701, Korea
pp. 640-646

Useful-skew clock optimization for multi-power mode designs (Abstract)

Hsuan-Ming Chou , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Hao Yu , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
pp. 647-650

ATree-based topology synthesis for on-chip network (Abstract)

Jason Cong , Computer Science Department, University of California, Los Angeles, Los Angeles, USA
Yuhui Huang , Computer Science Department, University of California, Los Angeles, Los Angeles, USA
Bo Yuan , Computer Science Department, University of California, Los Angeles, Los Angeles, USA
pp. 651-658

Formal verification of phase-locked loops using reachability analysis and continuization (Abstract)

Matthias Althoff , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Soner Yaldiz , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Akshay Rajhans , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Xin Li , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Bruce H. Krogh , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Larry Pileggi , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
pp. 659-666

MACACO: Modeling and analysis of circuits for approximate computing (Abstract)

Rangharajan Venkatesan , School of Electrical and Computer Engineering, Purdue University
Amit Agarwal , School of Electrical and Computer Engineering, Purdue University
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University
Anand Raghunathan , School of Electrical and Computer Engineering, Purdue University
pp. 667-673

Property-specific sequential invariant extraction for SAT-based unbounded model checking (Abstract)

Hu-Hsi Yeh , Department of Electrical Engineering / Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
Cheng-Yin Wu , Department of Electrical Engineering / Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
Chung-Yang (Ric) Huang , Department of Electrical Engineering / Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
pp. 674-678

Automatic formal verification of multithreaded pipelined microprocessors (Abstract)

Miroslav N. Velev , Aries Design Automation, LLC
Ping Gao , Aries Design Automation, LLC
pp. 679-686

Accelerating RTL simulation with GPUs (Abstract)

Hao Qian , Institute of Microelectronics, Tsinghua University, Beijing, 100084, China
Yangdong Deng , Institute of Microelectronics, Tsinghua University, Beijing, 100084, China
pp. 687-693

CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques (Abstract)

Sheng Li , Hewlett-Packard Labs
Ke Chen , University of Notre Dame
Jung Ho Ahn , Seoul National University
Jay B. Brockman , University of Notre Dame
Norman P. Jouppi , Hewlett-Packard Labs
pp. 694-701

A trace compression algorithm targeting power estimation of long benchmarks (Abstract)

Andrey Ayupov , Intel Corporation, Strategic CAD Labs
Steven Burns , Intel Corporation, Strategic CAD Labs
pp. 702-707

A theoretical probabilistic simulation framework for dynamic power estimation (Abstract)

L. Wang , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
M. Olbrich , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
E. Barke , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany
T. Buchner , IBM Deutschland Research & Development, Böblingen, Germany
M. Buhler , IBM Deutschland Research & Development, Böblingen, Germany
P. Panitz , IBM Deutschland Research & Development, Böblingen, Germany
pp. 708-715

Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management (Abstract)

Hai Wang , Department of Electrical Engineering, University of California, Riverside, CA 92521
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California, Riverside, CA 92521
Guangdeng Liao , Department of Computer Science and Engineering, University of California, Riverside, CA 92521
Rafael Quintanilla , Intel Corporation, Chandler, AZ 85226
Ashish Gupta , Intel Corporation, Chandler, AZ 85226
pp. 716-723

Gate sizing and device technology selection algorithms for high-performance industrial designs (Abstract)

Muhammet Mustafa Ozdal , Intel Corporation, Hillsboro, OR 97124
Steven Burns , Intel Corporation, Hillsboro, OR 97124
Jiang Hu , Texas A&M University, College Station, TX 77843
pp. 724-731

Improving dual V (Abstract)

Junjun Gu , University of Maryland, College Park, MD 20742
Gang Qu , University of Maryland, College Park, MD 20742
Lin Yuan , Synopsys Inc., Mountain View, CA 94043
Cheng Zhuo , University of Michigan Ann Arbor, MI 48109
pp. 732-735

The approximation scheme for peak power driven voltage partitioning (Abstract)

Jia Wang , Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, Michigan 49931
Xiaodao Chen , Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, Michigan 49931
Chen Liao , Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, Michigan 49931
Shiyan Hu , Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, Michigan 49931
pp. 736-741

Timing ECO optimization via Bézier curve smoothing and fixability identification (Abstract)

Hua-Yu Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
Iris Hui-Ru Jiang , Dept. of Electronics Engineering and Inst. of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
pp. 742-746

Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs (Abstract)

Vasileios Tenentes , Dept. of Computer Science, University of Ioannina
Xrysovalantis Kavousianos , Dept. of Computer Science, University of Ioannina
pp. 747-754

Post-silicon bug diagnosis with inconsistent executions (Abstract)

Andrew DeOrio , University of Michigan
Daya Shanker Khudia , University of Michigan
Valeria Bertacco , University of Michigan
pp. 755-761

On proving the efficiency of alternative RF tests (Abstract)

Nathan Kupp , Department of Electrical Engineering, Yale University, New Haven, CT 06511
Haralampos Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Felix Viallet, 38031 Grenoble, France
Petros Drineas , Department of Computer Science, Rensselaer Polytechnic Institute, Troy, NY 12180
Yiorgos Makris , Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX 75080
pp. 762-767

Statistical defect-detection analysis of test sets using readily-available tester data (Abstract)

Xiaochun Yu , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
R. D. (Shawn) Blanton , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
pp. 768-773

A robust architecture for post-silicon skew tuning (Abstract)

Mac Y. C. Kao , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
Kun-Ting Tsai , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
Shih-Chieh Chang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
pp. 774-778

A low-swing crossbar and link generator for low-power networks-on-chip (Abstract)

Chia-Hsin Owen Chen , Dept. of Electrical Engineering and Computer Science, Massachusettes Institute of Technology, Cambridge, MA 02139
Sunghyun Park , Dept. of Electrical Engineering and Computer Science, Massachusettes Institute of Technology, Cambridge, MA 02139
Tushar Krishna , Dept. of Electrical Engineering and Computer Science, Massachusettes Institute of Technology, Cambridge, MA 02139
Li-Shiuan Peh , Dept. of Electrical Engineering and Computer Science, Massachusettes Institute of Technology, Cambridge, MA 02139
pp. 779-786

Exploring heterogeneous NoC design space (Abstract)

Hui Zhao , Department of Computer Science and Engineering, The Pennsylvania State University
Mahmut Kandemir , Department of Computer Science and Engineering, The Pennsylvania State University
Wei Ding , Department of Computer Science and Engineering, The Pennsylvania State University
Mary Jane Irwin , Department of Computer Science and Engineering, The Pennsylvania State University
pp. 787-793

Robust passive hardware metering (Abstract)

Sheng Wei , Computer Science Department, University of California, Los Angeles (UCLA), Los Angeles, CA 90095
Ani Nahapetian , Computer Science Department, University of California, Los Angeles (UCLA), Los Angeles, CA 90095
Miodrag Potkonjak , Computer Science Department, University of California, Los Angeles (UCLA), Los Angeles, CA 90095
pp. 802-809
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