The Community for Technology Leaders
Computer-Aided Design, International Conference on (2008)
San Jose, CA, USA
Nov. 10, 2008 to Nov. 13, 2008
ISBN: 978-1-4244-2819-9
TABLE OF CONTENTS
Papers

Introduction (PDF)

pp. i-ii

Conference comittees (PDF)

pp. iii-vii

Foreword (PDF)

pp. viii

CAD for displays! (PDF)

Mary Lou Jepsen , Pixel Qi, USA
pp. x

What can brain researchers learn from computer engineers and vice versa? (PDF)

Dmitri Chklovskii , Janelia Farm, Howard Hughes Medical Institute, Ashburn, VA, USA
pp. x

Reliable system design: Models, metrics and design techniques (PDF)

Kishor Trivedi , Duke Univ., Durham, NC, USA
Subhasish Mitra , Stanford Univ., CA, USA
Ravishankar K. Iyer , Univ. of Illinois, Urbana-Champaign, USA
James W. Tschanz , Intel Corp., Hillsboro, OR, USA
pp. xi

Architecting parallel programs (PDF)

Kurt Keutzer , Univ. of California, Berkeley, USA
Joel Phillips , Cadence Research Labs, Berkeley, CA, USA
Michael Wrinn , Intel Corp., Hillsboro, OR, USA
pp. xi

Embedded software verification: Challenges and solutions (PDF)

Malay Ganai , NEC Labs America, Princeton, NJ, USA
Chao Wang , NEC Labs America, Princeton, NJ, USA
Daniel Kroening , Oxford Univ., United Kingdom
Shuvendu Lahiri , Microsoft Corp., Redmond, WA, USA
pp. xii

Nanolithography and CAD challenges for 32nm/22nm and beyond (PDF)

David Z. Pan , Univ. of Texas, Austin, USA
Stephen Renwick , Nikon Precision, Inc., Belmont, CA, USA
Judy Huckabay , Cadence Design Systems, Inc., San Jose, CA, USA
Vivek Singh , Intel Corp., San Jose, CA, USA
pp. xii

Challenges at 45nm and beyond (PDF)

Paul Villarrubia , IBM Corp., Austin, TX, USA
Sang Dhong , IBM Corp., Sunnyvale, CA, USA
Eric Soenen , Taiwan Semiconductor Mfg. Co., Austin, TX, USA
Dan Bailey , Advanced Micro Devices, Inc., Austin, TX, USA
Puneet Gupta , Univ. of California, Los Angeles, USA
pp. xiii

Mixed-signal simulation challenges and solutions (PDF)

William Walker , Fujitsu Labs, Ltd., Sunnyvale, CA, USA
Henry Chang , Designer¿s Guide Consulting, Los Altos, CA, USA
John Croix , Nascentric, Inc., Austin, TX, USA
John G. Maneatis , True Circuits, Inc., Los Altos, CA, USA
pp. xiii

More Moore: Foolish, feasible, or fundamentally different? (PDF)

Jerry Bautista , Intel Corp., Santa Clara, CA, USA
Rob Aitken , ARM, Sunnyvale, CA, USA
Wojceich Maly , Carnegie Mellon Univ., Pittsburgh, PA, USA
Jan Rabaey , Univ. of California, Berkeley, CA, USA
Andreas Kuehlmann , Cadence Design System, Berkeley, CA, USA
pp. xiii

Table of contents (PDF)

pp. xiv-xxv

Author index (PDF)

pp. xxvi-xxxiv

Copyright (PDF)

pp. xxxv

Network flow-based power optimization under timing constraints in MSV-driven floorplanning (Abstract)

Evangeline F. Y. Young , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
Qiang Ma , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
pp. 1-8

Linear constraint graph for floorplan optimization with soft blocks (Abstract)

Hai Zhou , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA
Jia Wang , Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, 60616, USA
pp. 9-15

A novel fixed-outline floorplanner with zero deadspace for hierarchical design (Abstract)

Satoshi Goto , Information Production and Systems, Waseda University, Kitakyushu, Japan, 808-0135
Jinian Bian , Dept. of Computer Science&Technology, Tsinghua University, Beijing, China, 100084
Chung-Kuan Cheng , Dept. of Computer Science&Engineering, University of California, San Diego, La Jolla, 92093-0404, USA
Sheqin Dong , Dept. of Computer Science&Technology, Tsinghua University, Beijing, China, 100084
Ou He , Dept. of Computer Science&Technology, Tsinghua University, Beijing, China, 100084
pp. 16-23

Synthesis from multi-cycle atomic actions as a solution to the timing closure problem (Abstract)

Arvind , Computer Science and Artificial Intelligence Lab, Massachusetts Institute of Technology, Cambridge, 02139, USA
Michal Karczmarek , Computer Science and Artificial Intelligence Lab, Massachusetts Institute of Technology, Cambridge, 02139, USA
pp. 24-31

To SAT or not to SAT: Ashenhurst decomposition in a large scale (Abstract)

Hsuan-Po Lin , Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
Ruei-Rung Lee , Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
Jie-Hong R. Jiang , Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
pp. 32-37

Boolean factoring and decomposition of logic networks (Abstract)

Robert Brayton , Department of EECS, University of California, Berkeley, USA
Satrajit Chatterjee , Intel Corporation, Strategic CAD Labs, Hillsboro, OR, USA
Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
pp. 38-44

On the numbers of variables to represent sparse logic functions (Abstract)

Tsutomu Sasao , Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan
pp. 45-51

Effective IR-drop reduction in at-speed scan testing using distribution-controlling X-Identification (Abstract)

Xiaoqing Wen , Kyushu Institute of Technology, Iizuka, Japan
Takashi Aikyo , STARC, Yokohama, Japan
Hideaki Ito , STARC, Yokohama, Japan
Hiroshi Furukawa , Kyushu Institute of Technology, Iizuka, Japan
Seiji Kajihara , Kyushu Institute of Technology, Iizuka, Japan
Kenji Noda , STARC, Yokohama, Japan
Yuta Yamato , Kyushu Institute of Technology, Iizuka, Japan
Kazumi Hatayama , STARC, Yokohama, Japan
Kohei Miyase , Kyushu Institute of Technology, Iizuka, Japan
pp. 52-58

Temperature-aware test scheduling for multiprocessor systems-on-chip (Abstract)

Robert P. Dick , EECS Department, Northwestern University, Evanston, IL 60208, USA
Li Shangz , ECE Department, University of Colorado at Boulder, 80305, USA
Thidapat Chantemy , CSE Department, University of Notre Dame, IN 46556, USA
Alok Choudhary , EECS Department, Northwestern University, Evanston, IL 60208, USA
Prabhat Kumar , EECS Department, Northwestern University, Evanston, IL 60208, USA
David R. Bild , EECS Department, Northwestern University, Evanston, IL 60208, USA
X. Sharon Huy , CSE Department, University of Notre Dame, IN 46556, USA
Sanchit Misra , CSE Department, University of Notre Dame, IN 46556, USA
pp. 59-66

On capture power-aware test data compression for scan-based testing (Abstract)

Xiaowei Li , Key Laboratory of Computer System and Architecture, ICT, CAS, Beijing, China
Yu Hu , Key Laboratory of Computer System and Architecture, ICT, CAS, Beijing, China
Yubin Zhang , CUhk REliable computing laboratory (CURE), Deptartment of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Jia Li , Key Laboratory of Computer System and Architecture, ICT, CAS, Beijing, China
Xiao Liu , CUhk REliable computing laboratory (CURE), Deptartment of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable computing laboratory (CURE), Deptartment of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 67-72

MAPS: Multi-Algorithm Parallel circuit Simulation (Abstract)

Xiaoji Ye , Department of ECE, Texas A&M University, College Station, 77843, USA
Sani Nassif , IBM Austin Research Laboratory, Austin, TX 78758, USA
Wei Dong , Department of ECE, Texas A&M University, College Station, 77843, USA
Peng Li , Department of ECE, Texas A&M University, College Station, 77843, USA
pp. 73-78

Yield-aware hierarchical optimization of large analog integrated circuits (Abstract)

Peng Li , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843, USA
Guo Yu , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843, USA
pp. 79-84

Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems (Abstract)

Jaijeet Roychowdhury , ECE Department, University of Minnesota, Twin Cities, USA
Chenjie Gu , ECE Department, University of Minnesota, Twin Cities, USA
pp. 85-92

Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure (Abstract)

Huan Ren , Dept. of ECE, University of Illinois-Chicago, USA
Shantanu Dutt , Dept. of ECE, University of Illinois-Chicago, USA
pp. 93-100

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization (Abstract)

Jiang Hu , Department of ECE, Texas A&M University, College Station, USA
Rupesh S. Shelar , Technology&Manufacturing Group, Intel Corporation Hillsboro, OR, USA
Yifang Liu , Department of ECE, Texas A&M University, College Station, USA
pp. 101-106

PaRS: Fast and near-optimal grid-based cell sizing for library-based design (Abstract)

Tai-Hsuan Wu , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engineering Dr., 53706, USA
Azadeh Davoodi , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engineering Dr., 53706, USA
pp. 107-111

A polynomial time approximation scheme for timing constrained minimum cost layer assignment (Abstract)

Shiyan Hu , Dept. of Electrical and Computer Engineering, Michigan Technological University, Houghton, 49931 USA
Zhuo Li , IBM Austin Research Laboratory, 11501 Burnet Road, Texas 78758 USA
Charles J. Alpert , IBM Austin Research Laboratory, 11501 Burnet Road, Texas 78758 USA
pp. 112-115

On the decreasing significance of large standard cells in technology mapping (Abstract)

Dennis Sylvester , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
David Blaauw , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
Jae-sun Seo , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
Igor L. Markov , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
pp. 116-121

Verification of arithmetic datapaths using polynomial function models and congruence solving (Abstract)

Sivaram Gopalakrishnan , ECE Dept., University of Utah, Salt Lake City, USA
Priyank Kalla , ECE Dept., University of Utah, Salt Lake City, USA
Namrata Shekhar , Synopsys Inc., Marlborough MA, USA
Neal Tew , ECE Dept., University of Utah, Salt Lake City, USA
pp. 122-128

Automated abstraction by incremental refinement in interpolant-based model checking (Abstract)

M. Murciano , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
P. Camurati , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
G. Cabodi , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
pp. 129-136

A succinct memory model for automated design debugging (Abstract)

Brian Keng , 1University of Toronto, ECE Department, ON M5S 3G4 Canada
Hratch Mangassarian , 1University of Toronto, ECE Department, ON M5S 3G4 Canada
Andreas Veneris , 1University of Toronto, ECE Department, ON M5S 3G4 Canada
pp. 137-142

The analysis of cyclic circuits with Boolean satisfiability (Abstract)

John Backes , Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. S.E., Minneapolis, 55455, USA
Brian Fett , Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. S.E., Minneapolis, 55455, USA
Marc D. Riedel , Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. S.E., Minneapolis, 55455, USA
pp. 143-148

System-level power estimation using an on-chip bus performance monitoring unit (Abstract)

Sangyoung Park , Dept. of EECS, Seoul National University, Korea
Youngjin Cho , Dept. of EECS, Seoul National University, Korea
Naehyuck Chang , Dept. of EECS, Seoul National University, Korea
Younghyun Kim , Dept. of EECS, Seoul National University, Korea
pp. 149-154

Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing (Abstract)

Massoud Pedram , University of Southern California, Department of Electrical Engineering, Los Angeles, 90089 U.S.A.
Mohammad Ghasemazar , University of Southern California, Department of Electrical Engineering, Los Angeles, 90089 U.S.A.
pp. 155-160

Accurate energy breakeven time estimation for run-time power gating (Abstract)

Wen-Ben Jone , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
Ranga Vemuri , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
Hao Xu , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
pp. 161-168

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits (Abstract)

Taewhan Kim , School of Electrical Engineering and Computer Science, Seoul National University, Korea
Deog-Kyoon Jeong , School of Electrical Engineering and Computer Science, Seoul National University, Korea
Yongho Lee , School of Electrical Engineering and Computer Science, Seoul National University, Korea
pp. 169-172

Efficient block-based parameterized timing analysis covering all potentially critical paths (Abstract)

Khaled R. Heloue , Department of ECE, University of Toronto, Ontario, Canada
Farid N. Najm , Department of ECE, University of Toronto, Ontario, Canada
Sari Onaissi , Department of ECE, University of Toronto, Ontario, Canada
pp. 173-180

Adjustment-based modeling for Statistical Static Timing Analysis with high dimension of variability (Abstract)

Azadeh Davoodi , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, 53706 USA
Tai-Hsuan Wu , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, 53706 USA
Lin Xie , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, 53706 USA
Jun Zhang , Department of Statistics, University of Wisconsin, Madison, 53706 USA
pp. 181-184

Post-silicon timing characterization by compressed sensing (Abstract)

Farinaz Koushanfar , ECE and CS Depts, Rice University, USA
Petros Boufounos , ECE Dept, Rice University, USA
Davood Shamsi , ECE Dept, Rice University, USA
pp. 185-189

Practical, fast Monte Carlo statistical static timing analysis: Why and how (Abstract)

Sonia Singhal , Synopsys Inc., CA, USA
Amith Singhee , IBM T J Watson Research Center, NY, USA
Rob A. Rutenbar , Carnegie Mellon University, PA, USA
pp. 190-195

On efficient Monte Carlo-based Statistical Static Timing Analysis of digital circuits (Abstract)

Javid Jaffari , Spry Design Automation, Waterloo, ON, Canada N2J 4P9
Mohab Anis , Spry Design Automation, Waterloo, ON, Canada N2J 4P9
pp. 196-203

Pyramids: An efficient computational geometry-based approach for timing-driven placement (Abstract)

Zhuo Li , IBM Austin Research Lab / 11501 Burnet Rd., TX 78758, USA
David A. Papa , University of Michigan / EECS Department / Ann Arbor, 48109, USA
David Z. Pan , University of Texas at Austin / Department of ECE, 78712, USA
Tao Luo , Magma Design Automation / Austin, TX 78759, USA
Charles J. Alpert , IBM Austin Research Lab / 11501 Burnet Rd., TX 78758, USA
C. N. Sze , IBM Austin Research Lab / 11501 Burnet Rd., TX 78758, USA
pp. 204-211

Guiding global placement with wire density (Abstract)

Venkataramanan Balakrishnan , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035 USA
Kalliopi Tsota , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035 USA
Cheng-Kok Koh , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035 USA
pp. 212-217

Constraint graph-based macro placement for modern mixed-size circuit designs (Abstract)

Hsin-Chen Chen , Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Yung-Chung Chang , Genesys Logic, Inc., Shindian City, Taipei County 231, Taiwan
Yi-Lin Chuang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 218-223

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits (Abstract)

Seungwhun Paik , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
Youngsoo Shin , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
Hyein Lee , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
pp. 224-229

A novel sequential circuit optimization with clock gating logic (Abstract)

Shih-Hung Weng , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Yu-Min Kuo , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
pp. 230-233

Scalable and scalably-verifiable sequential synthesis (Abstract)

Robert Brayton , Department of EECS, University of California, Berkeley, USA
Stephen Jang , Xilinx Inc., San Jose, CA, USA
Michael Case , Department of EECS, University of California, Berkeley, USA
Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
pp. 234-241

System-level thermal aware design of applications with uncertain execution time (Abstract)

Karam S. Chatha , Department of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
Sushu Zhang , Department of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
pp. 242-249

Proactive temperature balancing for low cost thermal management in MPSoCs (Abstract)

Tajana Simunic Rosing , University of California, San Diego, USA
Kenny C. Gross , Sun Microsystems, San Diego, USA
Ayse Kivilcim Coskun , University of California, San Diego, USA
pp. 250-257

A framework for predictive dynamic temperature management of microprocessor systems (Abstract)

Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01002, USA
Omer Khan , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01002, USA
pp. 258-263

A Voltage-Frequency Island aware energy optimization framework for networks-on-chip (Abstract)

Duo Ding , Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, USA
David Z. Pan , Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, USA
Wooyoung Jang , Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, USA
pp. 264-269

Statistical modeling of metal-gate Work-Function Variability in emerging device technologies and implications for circuit design (Abstract)

Kaustav Banerjee , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Vivek De , Circuit Research Lab, Intel Corporation, Hillsboro, OR 97124, USA
Hamed Dadgour , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
pp. 270-277

Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits (Abstract)

Chih-Hong Hwang , Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
Tien-Yeh Li , Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
Yiming Li , Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
Ta-Ching Yeh , Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
pp. 278-285

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects (Abstract)

Philip C. W. Ng , Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan, R. O. C.
Meng-Fu You , Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan, R. O. C.
Kuen-Yu Tsai , Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan, R. O. C.
Yi-Chang Lu , Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan, R. O. C.
pp. 286-291

Linear analysis of random process variability (Abstract)

Victoria Wang , University of California, Los Angeles, USA
Dejan Markovic , University of California, Los Angeles, USA
pp. 292-296

Design and optimization of a digital microfluidic biochip for protein crystallization (Abstract)

Tao Xu , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Vamsee K. Pamula , Advanced Liquid Logic, Inc., Research Triangle Park, NC 27560, USA
pp. 297-301

Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction (Abstract)

Kia Bazargan , Department of Electrical and Computer Engineering, University of Minnesota, USA
Hushrav D. Mogal , Department of Electrical and Computer Engineering, University of Minnesota, USA
pp. 302-305

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions (Abstract)

Ulf Schlichtmann , Institute for Electronic Design Automation, Technische Universität München, Germany
Helmut Grab , Institute for Electronic Design Automation, Technische Universität München, Germany
Martin Strasser , Institute for Electronic Design Automation, Technische Universität München, Germany
Frank M. Johannes , Institute for Electronic Design Automation, Technische Universität München, Germany
Michael Eick , Institute for Electronic Design Automation, Technische Universität München, Germany
pp. 306-313

Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example (Abstract)

Vladimir Stojanovic , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Ranko Sredojevic , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
pp. 314-321

Breaking the simulation barrier: SRAM evaluation through norm minimization (Abstract)

Lara Dolecek , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Masood Qazi , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Devavrat Shah , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Anantha Chandrakasan , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
pp. 322-329

Power supply noise aware workload assignment for multi-core systems (Abstract)

Aida Todri , UCSB, ECE Department, USA
Malgorzata Marek-Sadowska , UCSB, ECE Department, USA
Joseph Kozhaya , IBM TJ Watson Research Center, USA
pp. 330-337

NTHU-Route 2.0: A fast and stable global router (Abstract)

Yu-Ting Lee , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
Ting-Chi Wang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
Yen-Jung Chang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
pp. 338-343

FastRoute3.0: A fast and high quality global router based on virtual capacity (Abstract)

Chris Chu , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011 USA
Yue Xu , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011 USA
Yanheng Zhang , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011 USA
pp. 344-349

Multi-layer global routing considering via and wire capacities (Abstract)

Huang-Yu Chen , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Chin-Hsiung Hsu , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
pp. 350-355

Race analysis for SystemC using model checking (Abstract)

Daniel Kroening , Oxford University, Computing Laboratory, UK
Nicolas Blanc , ETH Zurich, Switzerland
pp. 356-363

MC-Sim: An efficient simulation tool for MPSoC designs (Abstract)

Adam Kaplan , Computer Science Department, University of California, Los Angeles, 90095, USA
Mishali Naik , Computer Science Department, University of California, Los Angeles, 90095, USA
Karthik Gururaj , Computer Science Department, University of California, Los Angeles, 90095, USA
Jason Cong , Computer Science Department, University of California, Los Angeles, 90095, USA
Guoling Han , Computer Science Department, University of California, Los Angeles, 90095, USA
Glenn Reinman , Computer Science Department, University of California, Los Angeles, 90095, USA
pp. 364-371

Verifying external interrupts of embedded microprocessor in SoC with on-chip bus (Abstract)

Ing-Jer Huang , Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
Fu-Ching Yang , Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
Jing-Kun Zhong , Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
pp. 372-377

SRAM dynamic stability: Theory, variability and analysis (Abstract)

Peng Li , Department of ECE, Texas A&M University, College Station, 77843 USA
Wei Dong , Department of ECE, Texas A&M University, College Station, 77843 USA
Garng M. Huang , Department of ECE, Texas A&M University, College Station, 77843 USA
pp. 378-385

Impulse sensitivity function analysis of periodic circuits (Abstract)

Brian S. Leibowitz , Rambus, Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
Jaeha Kim , Rambus, Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
Metha Jeeradit , Rambus, Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
pp. 386-391

Automated extraction of expert knowledge in analog topology selection and sizing (Abstract)

Michiel Steyaert , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
Georges Gielen , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
Pieter Palmers , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
Trent McConaghy , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
pp. 392-395

Importance sampled circuit learning ensembles for robust analog IC design (Abstract)

Peng Gao , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
Trent McConaghy , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
Georges Gielen , ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg 10, Belgium
pp. 396-399

Physical models for electron transport in graphene nanoribbons and their junctions (Abstract)

Azad Naeemi , Georgia Institute of Technology, 791 Atlantic Dr. Atlanta, 30332 USA
James D. Meindl , Georgia Institute of Technology, 791 Atlantic Dr. Atlanta, 30332 USA
pp. 400-405

Characterization and modeling of graphene field-effect devices (Abstract)

I. Meric , Department of Electrical Engineering, Columbia University, New York, 10027 USA
P. Kim , Department of Physics, Columbia University, New York, 10027 USA
K. L. Shepard , Department of Electrical Engineering, Columbia University, New York, 10027 USA
pp. 406-411

Graphene nanoribbon FETs: Technology exploration and CAD (Abstract)

Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Jing Guo , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
pp. 412-415

Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization (Abstract)

Taewhan Kim , School of Electrical Engineering and Computer Science, Seoul National University, Korea
Yesin Ryu , School of Electrical Engineering and Computer Science, Seoul National University, Korea
pp. 416-419

Decoupling capacitance allocation for timing with statistical noise model and timing analysis (Abstract)

Takashi Sato , Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17, Nagatsuta, Midori-ku, Yokohama, Japan
Takashi Enami , Dept. Information Systems Engineering, Osaka University, 1-5 Yamadaoka, Suita, Japan
Masanori Hashimoto , Dept. Information Systems Engineering, Osaka University, 1-5 Yamadaoka, Suita, Japan
pp. 420-425

Transition-aware decoupling-capacitor allocation in power noise reduction (Abstract)

TingTing Hwang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
Che-Yu Liu , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
Po-Yuan Chen , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
pp. 426-429

Placement based multiplier rewiring for cell-based designs (Abstract)

Fan Mo , Synplicity, USA
Robert K. Brayton , Synplicity, USA
pp. 430-433

Correct-by-construction microarchitectural pipelining (Abstract)

Timothy Kam , Strategic CAD Labs, Intel Corp., Hillsboro, Oregon, USA
Michael Kishinevsky , Strategic CAD Labs, Intel Corp., Hillsboro, Oregon, USA
Marc Galceran-Oms , Universitat Politècnica de Catalunya, Barcelona, Spain
Jordi Cortadella , Universitat Politècnica de Catalunya, Barcelona, Spain
pp. 434-441

Performance optimization of elastic systems using buffer resizing and buffer insertion (Abstract)

Jordi Cortadella , Univ. Politècnica de Catalunya, Barcelona, Spain
Dmitry Bufistov , Univ. Politècnica de Catalunya, Barcelona, Spain
Jorge Julvez , Univ. Politècnica de Catalunya, Barcelona, Spain
pp. 442-448

Performance estimation and slack matching for pipelined asynchronous architectures with choice (Abstract)

Gennette Gill , Dept. of Computer Science, Univ. of North Carolina, Chapel Hill, 27599, USA
Montek Singh , Dept. of Computer Science, Univ. of North Carolina, Chapel Hill, 27599, USA
Vishal Gupta , Dept. of Computer Science, Univ. of North Carolina, Chapel Hill, 27599, USA
pp. 449-456

Diastolic arrays: Throughput-driven reconfigurable computing (Abstract)

Srinivas Devadas , Massachusetts Institute of Technology, USA
G. Edward Suh , Cornell University, USA
Chih-Chi Cheng , National Taiwan University, Taiwan
Michel Kinsy , Massachusetts Institute of Technology, USA
Myong Hyon Cho , Massachusetts Institute of Technology, USA
pp. 457-464

Layout decomposition for double patterning lithography (Abstract)

Chul-Hong Park , ECE Department, UC San Diego, La Jolla, CA, USA
Xu Xu , Blaze DFM, Inc., Sunnyvale, CA, USA
Andrew B. Kahng , CSE Department, UC San Diego, La Jolla, CA, USA
Hailong Yao , CSE Department, UC San Diego, La Jolla, CA, USA
pp. 465-472

Electrically driven optical proximity correction based on linear programming (Abstract)

Shayak Banerjee , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Michael Orshansky , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Praveen Elakkumanan , IBM Corp., Hopewell Junction, NY, USA
Lars W. Liebmann , IBM Corp., Hopewell Junction, NY, USA
pp. 473-479

A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique (Abstract)

Yan Wang , Institute of Microelectronics, Tsinghua University, Beijing, China, 100084
Wei Xiong , Institute of Microelectronics, Tsinghua University, Beijing, China, 100084
Jinyu Zhang , Institute of Microelectronics, Tsinghua University, Beijing, China, 100084
Zhiping Yu , Institute of Microelectronics, Tsinghua University, Beijing, China, 100084
Min-Chun Tsai , Advanced Technology Group, Synopsys Inc., Mountain View, CA, 94043, USA
pp. 480-487

Overlay aware interconnect and timing variation modeling for Double Patterning Technology (Abstract)

David Z. Pan , Dept. of ECE, The University of Texas at Austin, 78712, USA
Jae-Seok Yang , Dept. of ECE, The University of Texas at Austin, 78712, USA
pp. 488-493

Exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinates (Abstract)

Ulrich Finkler , IBM T.J.Watson Res. Center, 1101 Kitchawan Rd. (rt. 134) 34-159, Yorktown Heights, NY, 10598 USA
Alexey Lvov , IBM T.J.Watson Res. Center, 1101 Kitchawan Rd. (rt. 134) 34-159, Yorktown Heights, NY, 10598 USA
pp. 494-498

BSG-Route: A length-matching router for general topology (Abstract)

Martin D. F. Wong , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Tan Yan , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
pp. 499-505

Double patterning technology friendly detailed routing (Abstract)

Yongchan Ban , Dept. of ECE, The University of Texas at Austin, 78712, USA
David Z. Pan , Dept. of ECE, The University of Texas at Austin, 78712, USA
Minsik Cho , Dept. of ECE, The University of Texas at Austin, 78712, USA
pp. 506-511

Routing for chip-package-board co-design considering differential pairs (Abstract)

Jia-Wei Fang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Kuan-Hsien Ho , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 512-517

Area-I/O flip-chip routing for chip-package co-design (Abstract)

Jia-Wei Fang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 518-522

Obstacle-avoiding rectilinear Steiner tree construction (Abstract)

Evangeline F. Y. Young , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
Liang Li , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
pp. 523-528

Evaluation of voltage interpolation to address process variations (Abstract)

Gu-Yeon Wei , School of Engineering and Applied Sciences Harvard University, Cambridge, MA 01238 USA
David Brooks , School of Engineering and Applied Sciences Harvard University, Cambridge, MA 01238 USA
Kevin Brownell , School of Engineering and Applied Sciences Harvard University, Cambridge, MA 01238 USA
pp. 529-536

Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors (Abstract)

Ravishankar Rao , Department of Computer Science and Engineering, Arizona State University, Tempe, 85281, USA
Sarma Vrudhula , Department of Computer Science and Engineering, Arizona State University, Tempe, 85281, USA
pp. 537-542

ROAdNoC: Runtime observability for an adaptive network on chip architecture (Abstract)

Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
Thomas Ebi , University of Karlsruhe, Chair for Embedded Systems, Germany
Mohammad Abdullah Al Faruque , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 543-548

FBT: Filled Buffer Technique to reduce code size for VLIW processors (Abstract)

Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
Talal Bonny , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 549-554

Advancing supercomputer performance through interconnection topology synthesis (Abstract)

Chung-Kuan Cheng , Department of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, 92093-0404, U.S.A.
Yi Zhu , Department of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, 92093-0404, U.S.A.
Michael Taylor , Department of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, 92093-0404, U.S.A.
Scott B. Baden , Department of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, 92093-0404, U.S.A.
pp. 555-558

Texture Filter Memory (Abstract)

Tushar Krishna , Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
Anjul Patney , Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
Preeti Ranjan Panda , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
B. V. N. Silpa , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
G. S. Visweswaran , Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
pp. 559-564

SPM management using Markov chain based data access prediction (Abstract)

Ozcan Ozturk , Bilkent University, Ankara, Turkey
Taylan Yemliha , Syracuse University, Syracuse, NY, USA
Mahmut Kandemir , Pennsylvania State University, University Park, USA
Shekhar Srikantaiah , Pennsylvania State University, University Park, USA
pp. 565-569

Process variation aware system-level task allocation using stochastic ordering of delay distributions (Abstract)

Elaheh Bozorgzadeh , University of California, Irvine, USA
Love Singhal , University of California, Irvine, USA
pp. 570-574

Game-theoretic timing analysis (Abstract)

Alexander Rakhlin , EECS Department, UC Berkeley, USA
Sanjit A. Seshia , EECS Department, UC Berkeley, USA
pp. 575-582

Integrated code and data placement in two-dimensional mesh based chip multiprocessors (Abstract)

Taylan Yemliha , Syracuse University, NY. USA
Mustafa Karakoy , Imperial College, London. UK
Mary Jane Irwin , Pennsylvania State University, University Park, PA. USA
Mahmut Kandemir , Pennsylvania State University, University Park, PA. USA
Shekhar Srikantaiah , Pennsylvania State University, University Park, PA. USA
pp. 583-588

Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches (Abstract)

Saibal Mukhopadhyay , Department of ECE, Georgia Institute of Technology, Atlanta, USA
Somnath Paul , Department of EECS, Case Western Reserve University, Cleveland, OH, USA
Swarup Bhunia , Department of EECS, Case Western Reserve University, Cleveland, OH, USA
pp. 589-592

On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications (Abstract)

Tamer Ragheb , Electrical and Computer Engineering Department, Rice University, Houston TX 77005 USA
Yehia Massoud , Electrical and Computer Engineering Department, Rice University, Houston TX 77005 USA
pp. 593-597

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links (Abstract)

Subhasish Mitra , Stanford University, California, Usa
Thomas H. Lee , Stanford University, California, Usa
Luca Benini , DEIS, University of Bologna, Italy
Shinobu Fujita , Toshiba, Japan
Igor Loi , DEIS, University of Bologna, Italy
pp. 598-602

ThermalScope: Multi-scale thermal analysis for nanometer-scale integrated circuits (Abstract)

Ronggui Yang , ME Department, University of Colorado at Boulder, 80309, U.S.A
Li Shang , ECE Department, University of Colorado at Boulder, 80309, U.S.A
Nicholas Allec , ECE Department, Queen¿s University, Kingston, ON K7L 3N6, Canada
Zyad Hassan , ECE Department, University of Colorado at Boulder, 80309, U.S.A
Robert P. Dick , EECS Department, Northwestern University, Evanston, IL 60208, U.S.A
pp. 603-610

Parameterized transient thermal behavioral modeling for chip multiprocessors (Abstract)

Eduardo H. Pacheco , Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA 95052 USA
Sheldon X.-D. Tan , Dept. of Electrical Engineering, University of California, Riverside, 92521 USA
Duo Li , Dept. of Electrical Engineering, University of California, Riverside, 92521 USA
Murli Tirumala , Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA 95052 USA
pp. 611-617

Temperature aware task sequencing and voltage scaling (Abstract)

Ramkumar Jayaseelan , Department of Computer Science, National University of Singapore, Singapore
Tulika Mitra , Department of Computer Science, National University of Singapore, Singapore
pp. 618-623

Statistical path selection for at-speed test (Abstract)

Vladimir Zolotov , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA
Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA
Hanif Fatemi , Synopsys Inc., Mountain View, CA 94043 USA
Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA
pp. 624-631

Power supply signal calibration techniques for improving detection resolution to hardware Trojans (Abstract)

Mohammad Tehranipoor , Department of Electrical and Computer Engineering, Univ. of Connecticut, USA
Jim Plusquellic , Department of Electrical and Computer Engineering, Univ. of New Mexico, USA
Reza M. Rad , Department of CSEE, Univ. of Maryland, Baltimore Campus, USA
Xiaoxiao Wang , Department of Electrical and Computer Engineering, Univ. of Connecticut, USA
pp. 632-639

Path-RO: A novel on-chip critical path delay measurement under process variations (Abstract)

Mohammad Tehranipoor , Dept. of ECE, University of Connecticut, USA
Xiaoxiao Wang , Dept. of ECE, University of Connecticut, USA
Ramyanshu Datta , Texas Instruments, USA
pp. 640-646

Multigrid on GPU: Tackling Power Grid Analysis on parallel SIMT platforms (Abstract)

Zhuo Feng , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843 USA
Peng Li , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843 USA
pp. 647-654

Efficient and accurate eye diagram prediction for high speed signaling (Abstract)

Ernest S. Kuh , Department of Electrical Engineering and Computer Science, UC Berkeley, CA, 94720, USA
Rui Shi , Department of Computer Science and Engineering, UC San Diego, La Jolla, CA, 92093, USA
Wenjian Yu , Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China
Chung-Kuan Cheng , Department of Computer Science and Engineering, UC San Diego, La Jolla, CA, 92093, USA
Yi Zhu , Department of Computer Science and Engineering, UC San Diego, La Jolla, CA, 92093, USA
pp. 655-661

A capacitance solver for incremental variation-aware extraction (Abstract)

Ibrahim M. Elfadel , Systems&Technology Group, IBM Corporation, USA
Tarek A. El-Moselhy , Research Lab in Electronics, Massachusetts Institute of Technology, USA
Luca Daniel , Research Lab in Electronics, Massachusetts Institute of Technology, USA
pp. 662-669

Lightweight secure PUFs (Abstract)

Miodrag Potkonjak , Computer Science Department, University of California, Los Angeles, 3532G Boelter Hall, 90095 USA
Mehrdad Majzoobi , Electrical and Computer Engineering Department, Rice University, 6100 Main, MS380, Houston, TX 77005 USA
Farinaz Koushanfar , Electrical and Computer Engineering Department, Rice University, 6100 Main, MS380, Houston, TX 77005 USA
pp. 670-673

Hardware protection and authentication through netlist level obfuscation (Abstract)

Swarup Bhunia , Dept. of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio 44106, USA
Rajat Subhra Chakraborty , Dept. of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio 44106, USA
pp. 674-677

MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm (Abstract)

Aleksandar Ignjatovic , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Jude Angelo Ambrose , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
pp. 678-684

Process variability-aware transient fault modeling and analysis (Abstract)

Kai-Chiang Wu , Electrical and Computer Engineering Department, Carnegie Mellon University, USA
Diana Marculescu , Electrical and Computer Engineering Department, Carnegie Mellon University, USA
Natasa Miskov-Zivanov , Electrical and Computer Engineering Department, Carnegie Mellon University, USA
pp. 685-690

STEEL: A technique for stress-enhanced standard cell library design (Abstract)

Dennis Sylvester , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
David Blaauw , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Vivek Joshi , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Brian T. Cline , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
pp. 691-697

A statistical approach for full-chip gate-oxide reliability analysis (Abstract)

Cheng Zhuo , Department of Electrical Engineering&Computer Science, University of Michigan, Ann Arbor, 48109 USA
David Blaauw , Department of Electrical Engineering&Computer Science, University of Michigan, Ann Arbor, 48109 USA
Dennis Sylvester , Department of Electrical Engineering&Computer Science, University of Michigan, Ann Arbor, 48109 USA
Kaviraj Chopra , Department of Electrical Engineering&Computer Science, University of Michigan, Ann Arbor, 48109 USA
pp. 698-705

Robust FPGA resynthesis based on fault-tolerant Boolean matching (Abstract)

Rupak Majumdar , Computer Science Department, University of California, Los Angeles, USA
Yu Hu , Electrical Engineering Department, University of California, Los Angeles, USA
Lei He , Electrical Engineering Department, University of California, Los Angeles, USA
Zhe Feng , Electrical Engineering Department, University of California, Los Angeles, USA
pp. 706-713

Fault tolerant placement and defect reconfiguration for nano-FPGAs (Abstract)

Amit Agarwal , Department of Computer Science, University of California at Los Angeles, USA
Brian Tagiku , Department of Computer Science, University of California at Los Angeles, USA
Jason Cong , Department of Computer Science, University of California at Los Angeles, USA
pp. 714-721

Thermal-aware reliability analysis for Platform FPGAs (Abstract)

Prasanth Mangalagiri , Department of Computer Science and Engineering, Pennsylvania State Universiy, State College, PA 16802, USA
Ramakrishnan Krishnan , Department of Computer Science and Engineering, Pennsylvania State Universiy, State College, PA 16802, USA
Yuan Xie , Department of Computer Science and Engineering, Pennsylvania State Universiy, State College, PA 16802, USA
Vijaykrishnan Narayanan , Department of Computer Science and Engineering, Pennsylvania State Universiy, State College, PA 16802, USA
Sungmin Bae , Department of Computer Science and Engineering, Pennsylvania State Universiy, State College, PA 16802, USA
pp. 722-727

Guaranteed stable projection-based model reduction for indefinite and unstable linear systems (Abstract)

Bradley N. Bond , Research Laboratory in Electronics, Massachusetts Institute of Technology, USA
Luca Daniel , Research Laboratory in Electronics, Massachusetts Institute of Technology, USA
pp. 728-735

Sparse Implicit Projection (SIP) for reduction of general many-terminal networks (Abstract)

Joel R. Phillips , Cadence Research Laboratories, USA
Dmitry Vasilyev , Massachusetts Institute of Technology, USA
Zuochang Ye , Cadence Research Laboratories, USA
Zhenhai Zhu , Cadence Research Laboratories, USA
pp. 736-743

Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method (Abstract)

Boyuan Yan , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Gengsheng Chen , ASIC&System State-Key-Lab, Microelectronics Dept., Fudan Univeristy, Shanghai, China, 200433
Lifeng Wu , Cadence Design Systems Inc., San Jose, CA 95134, USA
pp. 744-749

Integrated circuit design with NEM relays (Abstract)

Fred Chen , Department of EECS, Massachusetts Institute of Technology, Cambridge, 02139, USA
Dejan Markovic , EE Department, University of California, Los Angeles, 90095, USA
Elad Alon , Department of EECS, University of California, Berkeley, 94720, USA
Vladimir Stojanovic , Department of EECS, Massachusetts Institute of Technology, Cambridge, 02139, USA
Tsu-Jae King Liu , Department of EECS, University of California, Berkeley, 94720, USA
Hei Kam , Department of EECS, University of California, Berkeley, 94720, USA
pp. 750-757

Module locking in biochemical synthesis (Abstract)

Brian Fett , Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. S.E., Minneapolis, 55455, USA
Marc D. Riedel , Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. S.E., Minneapolis, 55455, USA
pp. 758-764

Robust reconfigurable filter design using analytic variability quantification techniques (Abstract)

Yehia Massoud , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Jamil Kawa , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Arthur Nieuwoudt , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
pp. 765-770

Using test data to improve IC quality and yield (Abstract)

Anne Gattiker , IBM Research, Austin Research Lab, TX, USA
pp. 771-777

Silicon feedback to improve frequency of high-performance microprocessors - an overview (Abstract)

Kip Killpack , Intel Corporation, Hillsboro, OR, USA
Pouria Bastani , University of California - Santa Barbara, USA
Chirayu Amin , Intel Corporation, Hillsboro, OR, USA
Chandramouli Kashyap , Intel Corporation, Hillsboro, OR, USA
pp. 778-782

Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking method (Abstract)

Ruiming Li , Sun Microsystems Inc., USA
Michel Laudes , Sun Microsystems Inc., USA
An-Jui Shey , Sun Microsystems Inc., USA
pp. 783-789

Constrained aggressor et selection for maximum coupling noise (Abstract)

Soroush Abbaspour , IBM Systems and Technology Group, EDA, Hopewell Jn, NY 12533, USA
Frank Borkam , IBM Systems and Technology Group, EDA, Hopewell Jn, NY 12533, USA
Alex Rubin , IBM Systems and Technology Group, EDA, Hopewell Jn, NY 12533, USA
Debjit Sinha , IBM Systems and Technology Group, EDA, Hopewell Jn, NY 12533, USA
Gregory Schaeffer , IBM Systems and Technology Group, EDA, Hopewell Jn, NY 12533, USA
pp. 790-796

Context-sensitive static transistor-level IR analysis (Abstract)

Yu Zhong , Dept. of Electrical and Computer Engineering, Univ. of Illinois at Urbana-Champaign, 61801, USA
Weiqing Guo , Silicon design CAD, Advanced Micro Devices, Sunnyvale, CA, 94085, USA
Tom Burd , Silicon design CAD, Advanced Micro Devices, Sunnyvale, CA, 94085, USA
pp. 797-802

Frequency-Aware PPV: A robust phase macromodel for accurate oscillator noise analysis (Abstract)

Xiaolue Lai , Cadence Design Systems, Inc. San Jose, CA, USA
pp. 803-806

Smoothed form of nonlinear phase macromodel for oscillators (Abstract)

M.M. Zharov , IPPM, Russian Academy of Sciences, Moscow, Russian Federation
B.J. Mulvaney , Freescale Semiconductor Inc., Austin, Texas, USA
S.G. Rusakov , IPPM, Russian Academy of Sciences, Moscow, Russian Federation
M.M. Gourary , IPPM, Russian Academy of Sciences, Moscow, Russian Federation
S.L. Ulyanov , IPPM, Russian Academy of Sciences, Moscow, Russian Federation
K.K. Gullapalli , Freescale Semiconductor Inc., Austin, Texas, USA
pp. 807-814

Comprehensive procedure for fast and accurate coupled oscillator network simulation (Abstract)

Jaijeet Roychowdhury , Department of Electrical and Computer Engineering, University of Minnesota, USA
Xiaolue Lai , Department of Electrical and Computer Engineering, University of Minnesota, USA
Prateek Bhansali , Department of Electrical and Computer Engineering, University of Minnesota, USA
Shweta Srivastava , Department of Electrical and Computer Engineering, University of Minnesota, USA
pp. 815-820
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