The Community for Technology Leaders
Computer-Aided Design, International Conference on (2007)
San Jose, CA USA
Nov. 4, 2007 to Nov. 8, 2007
ISSN: 1092-3152
ISBN: 978-1-4244-1381-2
TABLE OF CONTENTS

Introduction (PDF)

pp. i-ii

Conference committee (PDF)

pp. iii-vii

Foreword (PDF)

pp. viii

A fast and high-capacity electromagnetic solution for high- speed IC design (PDF)

Houle Gan , School of Electrical and Computer Engineering, Purdue University West Lafayette, IN 47907, USA
Dan Jiao , School of Electrical and Computer Engineering, Purdue University West Lafayette, IN 47907, USA
pp. 1-6

Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method (PDF)

Yang Yi , Texas A&M University, College Station, 77843, USA
Peng Li , Texas A&M University, College Station, 77843, USA
Vivek Sarin , Texas A&M University, College Station, 77843, USA
Weiping Shi , Texas A&M University, College Station, 77843, USA
pp. 7-10

Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach (PDF)

Arun V Sathanur , Department of Electrical Engineering, University of Washington, Seattle, USA
Ritochit Chakraborty , Department of Electrical Engineering, University of Washington, Seattle, USA
Vikram Jandhyala , Department of Electrical Engineering, University of Washington, Seattle, USA
pp. 11-17

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip (PDF)

Zhonghai Lu , Department of Electronic, Computer and Software Systems, Royal Institute of Technology, Sweden
Axel Jantsch , Department of Electronic, Computer and Software Systems, Royal Institute of Technology, Sweden
pp. 18-25

Run-time adaptive on-chip communication scheme (PDF)

Mohammad Abdullah Al Faruque , University of Karlsruhe, CES - Chair for Embedded Systems, Germany
Thomas Ebi , University of Karlsruhe, CES - Chair for Embedded Systems, Germany
Jorg Henkel , University of Karlsruhe, CES - Chair for Embedded Systems, Germany
pp. 26-31

Using functional independence conditions to optimize the performance of latency-insensitive systems (PDF)

Cheng-Hong Li , Department of Computer Science - Columbia University in the City of New York, USA
Luca P. Carloni , Department of Computer Science - Columbia University in the City of New York, USA
pp. 32-39

A geometric approach for early power grid verification using current constraints (PDF)

Imad A. Ferzli , Department of ECE University of Toronto, Ontario, Canada
Farid N. Najm , Department of ECE University of Toronto, Ontario, Canada
Lars Kruse , Magma Design Automation Eindhoven, The Netherlands
pp. 40-47

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks (PDF)

Ning Mi , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Pu Liu , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Jian Cui , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Yici Cai , Department of Computer Science and Technology, Tsinghua University, Beijing, 100081 China
Xianlong Hong , Department of Computer Science and Technology, Tsinghua University, Beijing, 100081 China
pp. 48-53

Parallel domain decomposition for simulation of large-scale power grids (PDF)

Kai Sun , Department of Computational and Applied Mathematics, Rice University, Houston, USA
Quming Zhou , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Danny C. Sorensen , Department of Computational and Applied Mathematics, Rice University, Houston, USA
pp. 54-59

Fast exact toffoli network synthesis of reversible logic (PDF)

Robert Wille , Group for Computer Architecture (Prof. Dr. Rolf Drechsler) University of Bremen, 28359, Germany
Daniel Grobe , Group for Computer Architecture (Prof. Dr. Rolf Drechsler) University of Bremen, 28359, Germany
pp. 60-64

A novel synthesis algorithm for reversible circuits (PDF)

Mehdi Saeedi , Quantum Design Automation Group, Computer Engineering Department Amirkabir University of Technology Tehran, Iran
Mehdi Sedighi , Quantum Design Automation Group, Computer Engineering Department Amirkabir University of Technology Tehran, Iran
Morteza Saheb Zamani , Quantum Design Automation Group, Computer Engineering Department Amirkabir University of Technology Tehran, Iran
pp. 65-68

Checking equivalence of quantum circuits and states (PDF)

George F. Viamontes , Lockheed Martin ATL, 3 Executive Campus Cherry Hill, NJ 08002, USA
Igor L. Markov , University of Michigan, Advanced Computer Architecture Lab., 2260 Hayward St., Ann Arbor, 48109-2121, USA
John P. Hayes , University of Michigan, Advanced Computer Architecture Lab., 2260 Hayward St., Ann Arbor, 48109-2121, USA
pp. 69-74

A self-adjusting clock tree architecture to cope with temperature variations (PDF)

Jieyi Long , Department of EECS, Northwestern University, Evanston, IL 60208, U.S.A.
Ja Chun Ku , Department of EECS, Northwestern University, Evanston, IL 60208, U.S.A.
Seda Ogrenci Memik , Department of EECS, Northwestern University, Evanston, IL 60208, U.S.A.
Yehea Ismail , Department of EECS, Northwestern University, Evanston, IL 60208, U.S.A.
pp. 75-82

Exploiting STI stress for performance (PDF)

Andrew B. Kahng , CSE Departments, University of California at San Diego, USA
Puneet Sharma , ECE Departments, University of California at San Diego, USA
Rasit O. Topaloglu , CSE Departments, University of California at San Diego, USA
pp. 83-90

Automating post-silicon debugging and repair (PDF)

Kai-hui Chang , EECS Department, University of Michigan, Ann Arbor, 48109-2121, USA
Igor L. Markov , EECS Department, University of Michigan, Ann Arbor, 48109-2121, USA
Valeria Bertacco , EECS Department, University of Michigan, Ann Arbor, 48109-2121, USA
pp. 91-98

Practical method for obtaining a feasible integer solution in hierarchical layout optimization (PDF)

Xiaoping Tang , IBM T.J. Watson Research, Yorktown Heights, NY 10598, USA
Xin Yuan , IBM Corp. Essex Jct., VT 05452, USA
Michael S. Gray , IBM Corp. Essex Jct., VT 05452, USA
pp. 99-104

Monte-carlo driven stochastic optimization framework for handling fabrication variability (PDF)

Vishal Khandelwal , Advanced Technology Group, Synopsys Inc., Hillsboro, OR 97124, USA
Ankur Srivastava , Department of ECE, University of Maryland College Park, 20742, USA
pp. 105-110

Gate sizing by lagrangian relaxation revisited (PDF)

Jia Wang , Electrical Engineering and Computer Science Northwestern University Evanston, IL 60208, USA
Debasish Das , Electrical Engineering and Computer Science Northwestern University Evanston, IL 60208, USA
Hai Zhou , Electrical Engineering and Computer Science Northwestern University Evanston, IL 60208, USA
pp. 111-118

An efficient algorithm for statistical circuit optimization using lagrangian relaxation (PDF)

I-Jye Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 119-124

Unified adaptivity optimization of clock and logic signals (PDF)

Shiyan Hu , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843, USA
Jiang Hu , Department of Electrical and Computer Engineering, Texas A&M University, College Station, 77843, USA
pp. 125-130

Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors (PDF)

Sivaram Gopalakrishnan , Electrical & Computer Engineering, University of Utah, Salt Lake City, 84112, USA
Priyank Kalla , Electrical & Computer Engineering, University of Utah, Salt Lake City, 84112, USA
M. Brandon Meredith , Mathematics & Statistics, Georgia State University, Atlanta, 30303, USA
Florian Enescu , Mathematics & Statistics, Georgia State University, Atlanta, 30303, USA
pp. 143-148

Enhancing design robustness with reliability-aware resynthesis and logic simulation (PDF)

Smita Krishnaswamy , Advanced Computer Architecture Lab, University of Michigan, USA
Stephen M. Plaza , Advanced Computer Architecture Lab, University of Michigan, USA
Igor L. Markov , Advanced Computer Architecture Lab, University of Michigan, USA
John P. Hayes , Advanced Computer Architecture Lab, University of Michigan, USA
pp. 149-154

Mapping model with Inter-array memory sharing for multidimensional signal processing (PDF)

Ilie I. Luican , Dept. of Computer Science, University of Illinois at Chicago, USA
Hongwei Zhu , ARM, Inc., Sunnyvale, CA, USA
Florin Balasa , Dept. of Computer Science, Southern Utah University, Cedar City, USA
pp. 160-165

Increasing data-bandwidth to instruction-set extensions through register clustering (PDF)

Kingshuk Karuri , Integrated Signal Processing Systems, RWTH Aachen University, 52056 Germany
Anupam Chattopadhyay , Integrated Signal Processing Systems, RWTH Aachen University, 52056 Germany
Manuel Hohenauer , Integrated Signal Processing Systems, RWTH Aachen University, 52056 Germany
Rainer Leupers , Integrated Signal Processing Systems, RWTH Aachen University, 52056 Germany
Gerd Ascheid , Integrated Signal Processing Systems, RWTH Aachen University, 52056 Germany
Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen University, 52056 Germany
pp. 166-171

Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design (PDF)

Philip Brisk , Processor Architecture Laboratory, Ecole Polytechnique Federale de Lausanne, Switzerland
Ajay K. Verma , Processor Architecture Laboratory, Ecole Polytechnique Federale de Lausanne, Switzerland
Paolo Ienne , Processor Architecture Laboratory, Ecole Polytechnique Federale de Lausanne, Switzerland
pp. 172-179

An efficient algorithm for time separation of events in concurrent systems (PDF)

Peggy B. McGee , Department of Computer Science Columbia University New York, 10027, USA
Steven M. Nowick , Department of Computer Science Columbia University New York, 10027, USA
pp. 180-187

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates (PDF)

Yu Hu , Electrical Engineering Department, UCLA, Los Angeles, CA 900951, USA
Satyaki Das , Research Laboratory, Xilinx Inc., 2100 Logic Dr. San Jose, CA 951242, USA
Steve Trimberger , Research Laboratory, Xilinx Inc., 2100 Logic Dr. San Jose, CA 951242, USA
Lei He , Electrical Engineering Department, UCLA, Los Angeles, CA 900951, USA
pp. 188-193

Device and architecture concurrent optimization for FPGA transient soft error rate (PDF)

Yan Lin , Electrical Engineering Department University of California, Los Angeles, USA
Lei He , Electrical Engineering Department University of California, Los Angeles, USA
pp. 194-198

Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering (PDF)

Georgios Karakonstantis , Purdue University , West Lafayette, USA
Nilanjan Banerjee , Purdue University , West Lafayette, USA
Kaushik Roy , Purdue University , West Lafayette, USA
Chaitali Chakrabarti , Arizona State University, Tempe, USA
pp. 199-204

Thermal-aware steiner routing for 3D stacked ICs (PDF)

Mohit Pathak , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Sung Kyu Lim , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
pp. 205-211

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs (PDF)

Roshan Weerasekera , ECS/ICT/KTH, ELECTRUM 229, 164 40 Kista, Sweden
Li-Rong Zheng , ECS/ICT/KTH, ELECTRUM 229, 164 40 Kista, Sweden
Dinesh Pamunuwa , Centre for Microsystems Engineering, Lancaster University, LA1 4YR, UK
Hannu Tenhunen , ECS/ICT/KTH, ELECTRUM 229, 164 40 Kista, Sweden
pp. 212-219

Strategies for improving the parametric yield and profits of 3D ICs (PDF)

Cesare Ferri , Division of Engineering, Brown University Providence, RI 02912, USA
Sherief Reda , Division of Engineering, Brown University Providence, RI 02912, USA
R. Iris Bahar , Division of Engineering, Brown University Providence, RI 02912, USA
pp. 220-226

Scalable exploration of functional dependency by interpolation and incremental SAT solving (Abstract)

Chih-Chun Lee , Nat. Taiwan Univ., Taipei
J.-H.R. Jiang , Nat. Taiwan Univ., Taipei
Chung-Yang Huang , Nat. Taiwan Univ., Taipei
pp. 227-233

Incremental learning approach and SAT model for boolean matching with don’t cares (PDF)

Kuo-Hua Wang , Dept. of Computer Science and Information Engineering, Fu Jen Catholic University Hsinchuang City, Taipei County 24205, Taiwan
Chung-Ming Chan , Dept. of Computer Science and Information Engineering, Fu Jen Catholic University Hsinchuang City, Taipei County 24205, Taiwan
pp. 234-239

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test (PDF)

Hratch Mangassarian , University of Toronto, ECE Department, ON M5S 3G4, USA
Andreas Veneris , University of Toronto, ECE Department, ON M5S 3G4, USA
Sean Safarpour , University of Toronto, ECE Department, ON M5S 3G4, USA
Marco Benedetti , LIFO, University of Orléans, BP 6759-45067, Cedex 2, France
Duncan Smith , University of Toronto, ECE Department, ON M5S 3G4, USA
pp. 240-245

The coming of age of physical synthesis (PDF)

Charles J. Alpert , Design Productivity Group IBM Research Austin, TX 78758, USA
Chris Chu , Department of ECE Iowa State University Ames, IA 50011, USA
Paul G. Villarrubia , Server and Technology Group IBM Corp. Austin, TX 78758, USA
pp. 246-249

An incremental learning framework for estimating signal controllability in unit-level verification (PDF)

Charles H.-P. Wen , Dept. of Communication Engineering, National Chiao-Tung University, Hsinchu, 300 Taiwan
Li-C. Wang , Dept. of Electrical and Computer Engineering, Univ. of California, Santa Barbara, 93106, USA
Jayanta Bhadra , Freescale Semiconductor Inc., Austin, TX 78729, USA
pp. 250-257

Stimulus generation for constrained random simulation (PDF)

Nathan Kitchen , University of California at Berkeley, USA
Andreas Kuehlmann , University of California at Berkeley, USA
pp. 258-265

Computation of minimal counterexamples by using black box techniques and symbolic methods (PDF)

Tobias Nopper , Institute of Computer Science, Albert-Ludwigs-University, D-79110 Freiburg, Germany
Christoph Scholl , Institute of Computer Science, Albert-Ludwigs-University, D-79110 Freiburg, Germany
Bernd Becker , Institute of Computer Science, Albert-Ludwigs-University, D-79110 Freiburg, Germany
pp. 273-280

Approximation algorithm for the temperature-aware scheduling problem (PDF)

Sushu Zhang , Department of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
Karam S. Chatha , Department of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
pp. 281-288

Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. (PDF)

Jian-Jia Chen , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan
Tei-Wei Kuo , Department of Computer Science and Information Engineering, Graduate Institute of Networking and Multimedia, National Taiwan University, Taiwan
pp. 289-294

The FAST methodology for high-speed SoC/computer simulation (PDF)

Derek Chiou , The University of Texas at Austin, USA
Dam Sunwoo , The University of Texas at Austin, USA
Joonsoo Kim , The University of Texas at Austin, USA
Nikhil Patil , The University of Texas at Austin, USA
William H. Reinhart , The University of Texas at Austin, USA
D. Eric Johnson , The University of Texas at Austin, USA
Zheng Xu , The University of Texas at Austin, USA
pp. 295-302

A novel SoC design methodology combining adaptive software and reconfigurable hardware (PDF)

Marco D. Santambrogio , DEI - Politecnico di Milano, Italy
Vincenzo Rana , DEI - Politecnico di Milano, Italy
Seda Ogrenci Memik , Northwestern University, USA
Umut A. Acar , Toyota Technological Institute at Chicago, USA
Donatella Sciuto , DEI - Politecnico di Milano, Italy
pp. 303-308

Hybrid cegar: combining variable hiding and predicate abstraction (PDF)

Chao Wang , NEC Laboratories America, USA
Hyondeuk Kim , University of Colorado, USA
Aarti Gupta , NEC Laboratories America, USA
pp. 310-317

Automated refinement checking of concurrent systems (PDF)

Sudipta Kundu , University of California, San Diego, La Jolla, 92093-0404, USA
Sorin Lerner , University of California, San Diego, La Jolla, 92093-0404, USA
Rajesh Gupta , University of California, San Diego, La Jolla, 92093-0404, USA
pp. 318-325

Inductive equivalence checking under retiming and resynthesis (PDF)

Jie-Hong R. Jiang , Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
Wei-Lun Hung , Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
pp. 326-333

A frequency-domain technique for statistical timing analysis of clock meshes (PDF)

Ruilin Wang , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN47907, USA
Cheng-Kok Koh , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN47907, USA
pp. 334-339

Clustering based pruning for statistical criticality computation under process variations (PDF)

Hushrav D Mogal , Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA
Haifeng Qian , IBM Research, Yorktown Heights, NY, USA
Sachin S Sapatnekar , Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA
Kia Bazargan , Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA
pp. 340-343

Timing budgeting under arbitrary process variations (PDF)

Ruiming Chen , NuCAD, Electrical Engineering and Computer Science, Northwestern University, USA
Hai Zhou , NuCAD, Electrical Engineering and Computer Science, Northwestern University, USA
pp. 344-349

Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping (PDF)

Yu Hu , Electrical Engineering Department, University of California, Los Angeles, USA
Victor Shih , Computer Science Department, University of California, Los Angeles, USA
Rupak Majumdar , Computer Science Department, University of California, Los Angeles, USA
Lei He , Electrical Engineering Department, University of California, Los Angeles, USA
pp. 350-353

Combinational and sequential mapping with priority cuts (PDF)

Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
Sungmin Cho , Department of EECS, University of California, Berkeley, USA
Satrajit Chatterjee , Department of EECS, University of California, Berkeley, USA
Robert Brayton , Department of EECS, University of California, Berkeley, USA
pp. 354-361

A general model for performance optimization of sequential systems (PDF)

Dmitry Bufistov , Univ. Politècnica de Catalunya Barcelona, Spain
Jordi Cortadella , Univ. Politècnica de Catalunya Barcelona, Spain
Mike Kishinevsky , Strategic CAD Lab, Intel Corp. Hillsboro, OR, USA
Sachin Sapatnekar , University of Minnesota Minneapolis, USA
pp. 362-369

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains (PDF)

Lei Cheng , Univ. of Illinois at UC, Champaign, IL, USA
Deming Chen , Univ. of Illinois at UC, Champaign, IL, USA
Martin D.F. Wong , Univ. of Illinois at UC, Champaign, IL, USA
Mike Hutton , Altera Corp., San Jose, CA, USA
Jason Govig , Altera Corp., San Jose, CA, USA
pp. 370-375

Skew aware polarity assignment in clock tree (PDF)

Po-Yuan Chen , Department of Computer Science National Tsing Hua University HsinChu, 300 Taiwan
Kuan-Hsien Ho , Department of Computer Science National Tsing Hua University HsinChu, 300 Taiwan
TingTing Hwang , Department of Computer Science National Tsing Hua University HsinChu, 300 Taiwan
pp. 376-379

Efficient multi-layer obstacle-avoiding rectilinear steiner tree construction (PDF)

Chung-Wei Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Shih-Lun Huang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Kai-Chi Hsu , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Meng-Xiang Li , Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
pp. 380-385

A simultaneous bus orientation and bused pin flipping algorithm (PDF)

Fan Mo , Synplicity, California, USA
Robert K. Brayton , University of California at Berkeley, USA
pp. 386-389

Optimal bus sequencing for escape routing in dense PCBs (PDF)

Hui Kong , Department of ECE, University of Illinois at U-C, Urbana, IL 61801, USA
Tan Yan , Department of ECE, University of Illinois at U-C, Urbana, IL 61801, USA
Martin D.F. Wong , Department of ECE, University of Illinois at U-C, Urbana, IL 61801, USA
Muhammet Mustafa Ozdal , Intel Corporation, Hillsboro, OR 97124, USA
pp. 390-395

Untangling twisted nets for bus routing (PDF)

Tan Yan , Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign, USA
Martin D.F. Wong , Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign, USA
pp. 396-400

Low-overhead design technique for calibration of maximum frequency at multiple operating points (PDF)

Somnath Paul , Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH., USA
Sivasubramaniam Krishnamurthy , Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH., USA
Hamid Mahmoodi , Electrical and Computer Engineering Department, San Francisco State University, CA., USA
Swarup Bhunia , Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH., USA
pp. 401-404

Variation-aware performance verification using at-speed structural test and statistical timing (PDF)

Vikram Iyengar , IBM Microelectronics, Essex Junction, VT, USA
Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Subbayyan Venkatesan , IBM Microelectronics, San Jose, CA., USA
Vladimir Zolotov , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
David Lackey , IBM Microelectronics, Essex Junction, VT, USA
Peter Habitz , IBM Microelectronics, Essex Junction, VT, USA
Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
pp. 405-412

Estimation of delay test quality and its application to test generation (PDF)

Seiji Kajihara , Kyushu Institute of Technology Iizuka, Japan
Shohei Morishima , Kyushu Institute of Technology Iizuka, Japan
Masahiro Yamamoto , Kyushu Institute of Technology Iizuka, Japan
Xiaoqing Wen , Kyushu Institute of Technology Iizuka, Japan
Masayasu Fukunaga , STARC Yokohama, Japan
Kazumi Hatayama , STARC Yokohama, Japan
Takashi Aikyo , STARC Yokohama, Japan
pp. 413-417

Efficient path delay test generation based on stuck-at test generation using checker circuitry (PDF)

Tsuyoshi Iwagaki , School of Information Science, Japan Advanced Institute of Science and Technology (JAIST) 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan
Satoshi Ohtake , Graduate School of Information Science, Nara Institute of Science and Technology (NAIST) Kansai Science City 630-0192, Japan
Mineo Kaneko , School of Information Science, Japan Advanced Institute of Science and Technology (JAIST) 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology (NAIST) Kansai Science City 630-0192, Japan
pp. 418-423

Timing variation-aware high-level synthesis (PDF)

Jongyoon Jung , School of Electrical Engineering and Computer Science Seoul National University, Korea
Taewhan Kim , School of Electrical Engineering and Computer Science Seoul National University, Korea
pp. 424-428

Early planning for clock skew scheduling during register binding (PDF)

Min Ni , Electrical Engineering and Computer Science Northwestern University, IL, USA
Seda Ogrenci Memik , Electrical Engineering and Computer Science Northwestern University, IL, USA
pp. 429-434

Compatibility path based binding algorithm for interconnect reduction in high level synthesis (PDF)

Taemin Kim , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, USA
Xun Liu , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, USA
pp. 435-441

Operation chaining asynchronous pipelined circuits (PDF)

Girish Venkataramani , ECE Department, Carnegie Mellon University Pittsburgh, PA 15213, USA
Seth C. Goldstein , School of Computer Science, Carnegie Mellon University, Pittsburgh, PA 15213, USA
pp. 442-449

Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization (PDF)

Xin Li , Department of ECE, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA 15213, USA
Brian Taylor , Department of ECE, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA 15213, USA
YuTsun Chien , Department of ECE, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA 15213, USA
Lawrence T. Pileggi , Department of ECE, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA 15213, USA
pp. 450-457

Sensitivity analysis for oscillators (PDF)

Igor Vytyaz , Oregon State University, Corvallis, Oregon, USA
David C. Lee , Berkeley Design Automation, Santa Clara, California, USA
Pavan Kumar Hanumolu , Oregon State University, Corvallis, Oregon, USA
Un-Ku Moon , Oregon State University, Corvallis, Oregon, USA
Kartikeya Mayaram , Oregon State University, Corvallis, Oregon, USA
pp. 458-463

Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling (PDF)

Guo Yu , Department of ECE, Texas A&M University, College Station, USA
Peng Li , Department of ECE, Texas A&M University, College Station, USA
pp. 464-469

Device-circuit co-optimization for mixed-mode circuit design via geometric programming (PDF)

Jintae Kim , Department of Electrical Engineering, University of Californica, Los Angeles, USA
Ritesh Jhaveri , Department of Electrical Engineering, University of Californica, Los Angeles, USA
Jason Woo , Department of Electrical Engineering, University of Californica, Los Angeles, USA
Chih-Kong Ken Yang , Department of Electrical Engineering, University of Californica, Los Angeles, USA
pp. 470-475

Modeling, optimization and control of rotary traveling-wave oscillator (PDF)

Cheng Zhuo , Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, 310027, China
Huafeng Zhang , Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, 310027, China
Rupak Samanta , Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, 77843, USA
Jiang Hu , Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, 77843, USA
Kangsheng Chen , Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, 310027, China
pp. 476-480

A methodology for fast and accurate yield factor estimation during global routing (PDF)

Subarna Sinha , Synopsys Inc., Mountain View, CA 94043, USA
Charles C. Chiang , Synopsys Inc., Mountain View, CA 94043, USA
pp. 481-487

Archer: a history-driven global routing algorithm (PDF)

Muhammet Mustafa Ozdal , Intel Corporation Hillsboro, OR 97124 USA
Martin D. F. Wong , Dept. of Electrical and Computer Engineering Univ. of Illinois at Urbana-Champaign, 61801 USA
pp. 488-495

High-performance routing at the nanometer scale (PDF)

Jarrod A. Roy , The University of Michigan, Department of EECS, 2260 Hayward Ave., Ann Arbor, 48109-2121, USA
Igor L. Markov , The University of Michigan, Department of EECS, 2260 Hayward Ave., Ann Arbor, 48109-2121, USA
pp. 496-502

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router (PDF)

Minsik Cho , Dept. of ECE, The University of Texas at Austin, Austin, TX 78712, USA
Katrina Lu , Dept. of ECE, The University of Texas at Austin, Austin, TX 78712, USA
Kun Yuan , Dept. of ECE, The University of Texas at Austin, Austin, TX 78712, USA
David Z. Pan , Dept. of ECE, The University of Texas at Austin, Austin, TX 78712, USA
pp. 503-508

Cachecompress: a novel approach for test data compression with cache for IP embedded cores (PDF)

Hao Fang , Microprocessor Research and Development Center of Peking University, China
Chenguang Tong , Microprocessor Research and Development Center of Peking University, China
Bo Yao , Microprocessor Research and Development Center of Peking University, China
Xiaodi Song , Microprocessor Research and Development Center of Peking University, China
Xu Cheng , Microprocessor Research and Development Center of Peking University, China
pp. 509-512

A hybrid scheme for compacting test responses with unknown values (PDF)

Mango C.-T. Chao , Dept. of Electronics Engineering, National Chiao Tung Univ., Hsinchu, Taiwan
Kwang-Ting Cheng , Dept. of ECE, UC Santa Barbara, Santa Barbara, CA, USA
Seongmoon Wang , NEC Labs. America, Princeton, NJ, USA
Srimat T. Chakradhar , NEC Labs. America, Princeton, NJ, USA
Wen-Long Wei , NEC Labs. America, Princeton, NJ, USA
pp. 513-519

A selective pattern-compression scheme for power and test-data reduction (PDF)

Chia-Yi Lin , Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan
Hung-Ming Chen , Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan
pp. 520-525

Methodology for low power test pattern generation using activity threshold control logic (PDF)

Srivaths Ravi , Texas Instruments (India) Pvt. Ltd., Bangalore, 560 093 India
V. R. Devanathan , Texas Instruments (India) Pvt. Ltd., Bangalore, 560 093 India
Rubin Parekhji , Texas Instruments (India) Pvt. Ltd., Bangalore, 560 093 India
pp. 526-529

ECO timing optimization using spare cells (PDF)

Yen-Pin Chen , Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Jia-Wei Fang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 530-535

Timing optimization by restructuring long combinatorial paths (PDF)

Jeurgen Werber , Research Institute for Discrete Mathematics, University of Bonn, Lennéstraße 2, 53111 Bonn, Germany
Dieter Rautenbach , Department for Mathematics and Science, Technical University of Ilmenau, Weimarer Straße 26, 98693 Ilmenau, Germany
Christian Szegedy , Cadence Berkeley Labs, 1996 University Ave, Berkeley, CA 94704, USA
pp. 536-543

Engineering change using spare cells with constant insertion (PDF)

Yu-Min Kuo , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Ya-Ting Chang , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Malgorzata Marek-Sadowska , Department of ECE, University of California, Santa Barbara, CA, USA
pp. 544-547

Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization (PDF)

Lin Yuan , Synopsys, Inc., Mountain View, CA, USA
Gang Qu , Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies, University of Maryland, College Park, MD, USA
pp. 548-551

Equalized interconnects for on-chip networks: modeling and optimization framework (PDF)

Byungsub Kim , Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Vladimir Stojanovic , Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
pp. 552-559

Intsim: a CAD tool for optimization of multilevel interconnect networks (PDF)

Deepak C. Sekar , Georgia Institute of Technology, USA
Azad Naeemi , Georgia Institute of Technology, USA
Reza Sarvari , Georgia Institute of Technology, USA
Jeffrey A. Davis , Georgia Institute of Technology, USA
James D. Meindl , Georgia Institute of Technology, USA
pp. 560-567

A fast band-matching technique for interconnect inductance modeling (PDF)

Hong Li , Synopsys Inc., Mountain View, CA 94043, USA
Jitesh Jain , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035, USA
Cheng-Kok Koh , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035, USA
Venkataramanan Balakrishnan , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035, USA
pp. 568-571

Formal verification at higher levels of abstraction (PDF)

Daniel Kroening , Oxford University Computing Laboratory, USA
Sanjit A. Seshia , UC Berkeley, USA
pp. 572-578

Analog placement with common centroid constraints (PDF)

Qiang Ma , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
Evangeline F. Y. Young , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
K. P. Pun , Department of Electronic Engineering, The Chinese University of Hong Kong, China
pp. 579-585

Temperature aware microprocessor floorplanning considering application dependent power load (PDF)

Chun-Ta Chu , Department of Electrical Engineering, University of California at Los Angeles, 90095, USA
Xinyi Zhang , Department of Electrical Engineering, University of California at Los Angeles, 90095, USA
Lei He , Department of Electrical Engineering, University of California at Los Angeles, 90095, USA
Tom Tong Jing , Department of Electrical Engineering, University of California at Los Angeles, 90095, USA
pp. 586-589

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits (PDF)

Pingqiang Zhou , CS Department, Tsinghua University, Beijing, 100084, China
Yuchun Ma , CS Department, Tsinghua University, Beijing, 100084, China
Zhouyuan Li , Advanced Technology Group, Synopsys, Inc., Beijing, China
Robert P. Dick , EECS Department, Northwestern University, Evanston, IL 60208, U.S.A.
Li Shang , ECE Department, Queen¿s University, Kingston, ON K7L 3N6, Canada
Hai Zhou , EECS Department, Northwestern University, Evanston, IL 60208, U.S.A.
Xianlong Hong , CS Department, Tsinghua University, Beijing, 100084, China
Qiang Zhou , CS Department, Tsinghua University, Beijing, 100084, China
pp. 590-597

Variation-aware task allocation and scheduling for MPSoC (PDF)

Feng Wang , Pennsylvania State University, University Park, PA, 16802, USA
C. Nicopoulos , Pennsylvania State University, University Park, PA, 16802, USA
Xiaoxia Wu , Pennsylvania State University, University Park, PA, 16802, USA
Yuan Xie , Pennsylvania State University, University Park, PA, 16802, USA
N. Vijaykrishnan , Pennsylvania State University, University Park, PA, 16802, USA
pp. 598-603

A design flow dedicated to multi-mode architectures for DSP applications (PDF)

Cyrille Chavet , STMicroelectronics, Crolles, France
Caaliph Andriamisaina , LESTER Lab, CNRS FRE 2734, UBS University, France
Philippe Coussy , LESTER Lab, CNRS FRE 2734, UBS University, France
Emmanuel Casseau , R2D2-IRISA Lab, CNRS UMR 6074, Rennes 1 University, France
Emmanuel Juin , LESTER Lab, CNRS FRE 2734, UBS University, France
Pascal Urard , STMicroelectronics, Crolles, France
Eric Martin , LESTER Lab, CNRS FRE 2734, UBS University, France
pp. 604-611

The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip (PDF)

Yi Wang , The Center for Advanced Computer Studies, University of Louisiana at Lafayette, LA 70504, USA
Dan Zhao , The Center for Advanced Computer Studies, University of Louisiana at Lafayette, LA 70504, USA
pp. 612-617

Sparse and passive reduction of massively coupled large multiport interconnects (PDF)

Natalie Nakhla , Department of Electronics, Carleton University, Ottawa, Canada
Michel Nakhla , Department of Electronics, Carleton University, Ottawa, Canada
Ram Achar , Department of Electronics, Carleton University, Ottawa, Canada
pp. 622-626

Analysis of large clock meshes via Harmonic-weighted model order reduction and port sliding (PDF)

Xiaoji Ye , Department of ECE, Texas A&M University, College Station, 77843 USA
Peng Li , Department of ECE, Texas A&M University, College Station, 77843 USA
Min Zhao , Freescale Semiconductor, Inc, Austin, TX 78729, USA
Rajendran Panda , Freescale Semiconductor, Inc, Austin, TX 78729, USA
Jiang Hu , Department of ECE, Texas A&M University, College Station, 77843 USA
pp. 627-631

Principle Hessian Direction based parameter reduction with process variation (PDF)

Alex Mitev , Electrical Computer Engineering Department, University of Arizona, 1230 E. Speedway Tucson, 85721 U.S.A
Michael Marefat , Electrical Computer Engineering Department, University of Arizona, 1230 E. Speedway Tucson, 85721 U.S.A
Dongsheng Ma , Electrical Computer Engineering Department, University of Arizona, 1230 E. Speedway Tucson, 85721 U.S.A
Janet M. Wang , Electrical Computer Engineering Department, University of Arizona, 1230 E. Speedway Tucson, 85721 U.S.A
pp. 632-637

MOSFET Modeling for 45nm and Beyond (PDF)

Yu Cao , Department of Electrical Engineering, USA
Colin McAndrew , Freescale Semiconductor, Tempe, AZ 85284-1801, USA
pp. 638-643

Voltage island-driven floorplanning (PDF)

Qiang Ma , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong
Evangeline F. Y. Young , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong
pp. 644-649

An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning (PDF)

Wan-Ping Lee , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Hung-Yi Liu , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 650-655

Module assignment for pin-limited designs under the stacked-Vdd paradigm (PDF)

Yong Zhan , Department of Electrical and Computer Engineering, University of Minnesota, USA
Tianpei Zhang , Department of Electrical and Computer Engineering, University of Minnesota, USA
Sachin S. Sapatnekar , Department of Electrical and Computer Engineering, University of Minnesota, USA
pp. 656-659

Yield-driven near-threshold SRAM design (PDF)

Gregory K. Chen , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
David Blaauw , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
Trevor Mudge , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
Dennis Sylvester , Department of EECS, University of Michigan, Ann Arbor, 48109, USA
Nam Sung Kim , Microprocessor Technology Lab, Intel Corporation, Hillsboro, OR 97124 USA
pp. 660-666

Soft-edge flip-flops for improved timing yield: design and optimization (PDF)

Vivek Joshi , University of Michigan, Ann Arbor, USA
David Blaauw , University of Michigan, Ann Arbor, USA
Dennis Sylvester , University of Michigan, Ann Arbor, USA
pp. 667-673

Remote activation of ICs for piracy prevention and digital right management (PDF)

Yousra Alkabani , Computer Science Dept., Rice University, USA
Farinaz Koushanfar , Electrical & Computer Engineering and Computer Science Depts., Rice University, USA
Miodrag Potkonjak , Computer Science Dept., University of California, Los Angeles, USA
pp. 674-677

A nonlinear cell macromodel for digital applications (PDF)

Chandramouli Kashyap , Strategic CAD Labs, Intel Corporation, Hillsboro, OR 97124, U.S.A
Chirayu Amin , Strategic CAD Labs, Intel Corporation, Hillsboro, OR 97124, U.S.A
Noel Menezes , Strategic CAD Labs, Intel Corporation, Hillsboro, OR 97124, U.S.A
Eli Chiprout , Strategic CAD Labs, Intel Corporation, Hillsboro, OR 97124, U.S.A
pp. 678-685

Including inductance in static timing analysis (PDF)

Ahmed Shebaita , EECS Department, Northwestern University Evanston, IL 60208, U.S.A
Dusan Petranovic , Mentor Graphics, Wilsonville, OR 97070, U.S.A
Yehea Ismail , EECS Department, Northwestern University Evanston, IL 60208, U.S.A
pp. 686-691

A robust finite-point based gate model considering process variations (PDF)

Alex Mitev , Department of Electrical and Computer Engineering, University of Arizona at Tucson, U.S.A
Dinesh Ganesan , Department of Electrical Engineering, Arizona State University, Tempe, U.S.A
Dheepan Shanmugasundaram , Department of Electrical and Computer Engineering, University of Arizona at Tucson, U.S.A
Yu Cao , Department of Electrical Engineering, Arizona State University, Tempe, U.S.A
Janet M. Wang , Department of Electrical and Computer Engineering, University of Arizona at Tucson, U.S.A
pp. 692-697

Victim alignment in crosstalk aware timing analysis (PDF)

Ravikishore Gandikota , Department of EECS, University of Michigan, Ann Arbor, U.S.A
Kaviraj Chopra , Department of EECS, University of Michigan, Ann Arbor, U.S.A
David Blaauw , Department of EECS, University of Michigan, Ann Arbor, U.S.A
Dennis Sylvester , Department of EECS, University of Michigan, Ann Arbor, U.S.A
Murat Becer , CLK Design Automation, Littleton, MA, U.S.A
Joao Geada , CLK Design Automation, Littleton, MA, U.S.A
pp. 698-704

Compact modeling of variational waveforms (PDF)

V. Zolotov , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, U.S.A
J. Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, U.S.A
S. Abbaspour , IBM Electronic Design Automation, East Fishkill, NY, U.S.A
D. J. Hathaway , IBM Electronic Design Automation, Essex Junction, VT, USA
C. Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY, U.S.A
pp. 705-712

Multi-layer interconnect performance corners for variation-aware timing analysis (PDF)

Frank Huebbers , EECS Dept., Northwestern U., Evanston, IL 60208, U.S.A
Ali Dasdan , Yahoo!, Synnyvale, CA 94089, U.S.A
Yehea Ismail , EECS Dept., Northwestern U., Evanston, IL 60208, U.S.A
pp. 713-718

An efficient method for statistical circuit simulation (Abstract)

F. Liu , IBM Austin Res. Lab, Austin
pp. 719-724

A methodology for timing model characterization for statistical static timing analysis (PDF)

Zhuo Feng , Department of ECE, Texas A&M University, College Station, 77843, U.S.A
Peng Li , Department of ECE, Texas A&M University, College Station, 77843, U.S.A
pp. 725-729

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance (PDF)

Kunhyuk Kang , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, U.S.A
Sang Phill Park , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, U.S.A
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, U.S.A
Muhammad A. Alam , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, U.S.A
pp. 730-734

An efficient method to identify critical gates under circuit aging (PDF)

Wenping Wang , Department of Electrical Engineering, Arizona State University, Tempe, 85287, U.S.A
Zile Wei , Department of EECS, University of California, Berkeley, 94720, U.S.A
Shengqi Yang , Intel Corporation, Chandler, AZ 85226, U.S.A
Yu Cao , Department of Electrical Engineering, Arizona State University, Tempe, 85287, U.S.A
pp. 735-740

The effect of process variation on device temperature in finFET circuits (PDF)

Jung Hwan Choi , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Jayathi Murthy , School of Mechanical Engineering, Purdue University, West Lafayette, IN 47907, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
pp. 747-751

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips (PDF)

Ping-Hung Yuh , Department of Computer Science and Information Engineering, National Taiwan University, Taipei 106, Taiwan
Chia-Lin Yang , Department of Computer Science and Information Engineering, National Taiwan University, Taipei 106, Taiwan
Yao-Wen Chang , Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 752-757

Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture (PDF)

Chen Dong , Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA
Deming Chen , Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA
Sansiri Tanachutiwat , Department of Electrical and Computer Engineering, Indiana University-Purdue University at Indianapolis, USA
Wei Wang , Department of Electrical and Computer Engineering, Indiana University-Purdue University at Indianapolis, USA
pp. 758-764

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays (PDF)

M. Haykel Ben Jamaa , Integrated Systems Laboratory (LSI), EPFL, 1015 Lausanne, Switzerland
David Atienza , Integrated Systems Laboratory (LSI), EPFL, 1015 Lausanne, Switzerland
Giovanni De Micheli , Integrated Systems Laboratory (LSI), EPFL, 1015 Lausanne, Switzerland
Kirsten E. Moselund , Electronics Laboratory (LEG), EPFL, 1015 Lausanne, Switzerland
Didier Bouvet , Electronics Laboratory (LEG), EPFL, 1015 Lausanne, Switzerland
Adrian M. Ionescu , Electronics Laboratory (LEG), EPFL, 1015 Lausanne, Switzerland
Yusuf Leblebici , Microelectronic Systems Laboratory (LSM), EPFL, 1015 Lausanne, Switzerland
pp. 765-772

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems (PDF)

Susmit Biswas , University of California, Santa Barbara, 93117, USA
Gang Wang , University of California, Santa Barbara, 93117, USA
Ryan Kastner , University of California, Santa Barbara, 93117, USA
Frederic T. Chong , University of California, Santa Barbara, 93117, USA
Tzvetan S. Metodi , University of California, Davis, 95616, USA
pp. 773-778

An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon (PDF)

Yu-Ting Chen , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Da-Cheng Juan , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Ming-Chao Lee , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang , Department of CS, National Tsing Hua University, Hsinchu, Taiwan
pp. 779-782

Analysis and optimization of power-gated ICs with multiple power gating configurations (PDF)

Aida Todri , UCSB, ECE Department, Taiwan
Malgorzata Marek-Sadowska , UCSB, ECE Department, Taiwan
Shih-Chieh Chang , NTHU, CS Department, Taiwan
pp. 783-790

Sizing and placement of charge recycling transistors in MTCMOS circuits (PDF)

Ehsan Pakbaznia , Dep. of Electrical Engineering, University of Southern California, Los Angeles, U.S.A.
Massoud Pedram , Dep. of Electrical Engineering, University of Southern California, Los Angeles, U.S.A.
Farzan Fallah , Fujitsu Labs of America, Sunnyvale, U.S.A.
pp. 791-796

Minimizing leakage power in sequential circuits by using mixed vt flip-flops (PDF)

Jaehyun Kim , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
Youngsoo Shin , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
pp. 797-802

Efficient decoupling capacitance budgeting considering operation and process variations (PDF)

Yiyu Shi , Electrical Engineering Dept., UCLA, Los Angeles, California, 90024, USA
Chunchen Liu , Electrical Engineering Dept., UCLA, Los Angeles, California, 90024, USA
Lei He , Electrical Engineering Dept., UCLA, Los Angeles, California, 90024, USA
Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, New York, 10598, USA
pp. 803-810

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs (PDF)

Mikhail Popovich , Department of Electrical and Computer Engineering, University of Rochester, New York 14627, USA
Eby G. Friedman , Department of Electrical and Computer Engineering, University of Rochester, New York 14627, USA
Radu M. Secareanu , MMSTL, Freescale Semiconductor, Tempe, Arizona 85284, USA
Olin L. Hartin , MMSTL, Freescale Semiconductor, Tempe, Arizona 85284, USA
pp. 811-816

A novel technique for incremental analysis of on-chip power distribution networks (PDF)

Yuhong Fu , Freescale Semiconductor Inc., Austin, TX, USA
Rajendran Panda , Freescale Semiconductor Inc., Austin, TX, USA
Ben Reschke , Freescale Semiconductor Inc., Austin, TX, USA
Savithri Sundareswaran , Freescale Semiconductor Inc., Austin, TX, USA
Min Zhao , Freescale Semiconductor Inc., Austin, TX, USA
pp. 817-823

Architectural power models for sram and cam structures based on hybrid analytical/empirical techniques (PDF)

Xiaoyao Liang , School of Engineering and Applied Sciences, Harvard University, 33 Oxford Street, Cambridge MA 02138 USA
Kerem Turgay , School of Engineering and Applied Sciences, Harvard University, 33 Oxford Street, Cambridge MA 02138 USA
David Brooks , School of Engineering and Applied Sciences, Harvard University, 33 Oxford Street, Cambridge MA 02138 USA
pp. 824-830

Novel wire density driven full-chip routing for CMP variation control (PDF)

Huang-Yu Chen , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Szu-Jui Chou , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Sheng-Lung Wang , Synopsys, Inc, Taipei, Taiwan
pp. 831-838

Accurate detection for process-hotspots with vias and incomplete specification (PDF)

Jingyu Xu , Synopsys Inc., Mountain View, CA 94043, USA
Subarna Sinha , Synopsys Inc., Mountain View, CA 94043, USA
Charles C. Chiang , Synopsys Inc., Mountain View, CA 94043, USA
pp. 839-846

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction (PDF)

Peng Yu , The Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
David Z. Pan , The Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
pp. 847-853

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation (PDF)

Peng Yu , The Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
David Z. Pan , The Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
pp. 854-859

Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions (PDF)

Bradley N Bond , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, 02139, USA
Luca Daniel , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, 02139, USA
pp. 860-867

Parameterized model order reduction via a two-directional Arnoldi process (PDF)

Yung-Ta Li , Dept. of Mathematics, University of California, Davis, 95616, USA
Zhaojun Bai , Dept. of Computer Science, and Dept. of Mathematics, University of California, Davis, 95616, USA
Yangfeng Su , School of Mathematical Sciences, Fudan University, Shanghai 200433, China
Xuan Zeng , ASIC & System State Key Lab., Fudan University, Shanghai 200433, China
pp. 868-873

Efficient VCO phase macromodel generation considering statistical parametric variations (PDF)

Wei Dong , Department of ECE, Texas A&M University, College Station, TX 77843, USA
Zhuo Feng , Department of ECE, Texas A&M University, College Station, TX 77843, USA
Peng Li , Department of ECE, Texas A&M University, College Station, TX 77843, USA
pp. 874-878

Bounding L2 gain system error generated by approximations of the nonlinear vector field (PDF)

Kin Cheong Sou , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Alexandre Megretski , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
Luca Daniel , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
pp. 879-886

Variable domain transformation for linear PAC analysis of mixed-signal systems (PDF)

Jaeha Kim , Rambus, Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
Kevin D. Jones , Rambus, Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
Mark A. Horowitz , Rambus, Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
pp. 887-894
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